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Ferroelectric (FE)-HfO2-based FETs (FEFETs) are one of the most promising candidates for emerging memories. However, the FE material suffers from a unique reliability phenomenon known as imprint: the coercive voltage shifts during data retention, which has been regarded as a major issue for memory operation, while the mechanism causing it is still under research. In this article, imprint and its recovery in FE-HfO2 are investigated in detail by comprehensive electrical measurements to reveal its underlying mechanism including the cause of asymmetric coercive voltage shifts. The recovery measurements clarify that domain switching is indispensable for the recovery from imprint. The subloop imprint effect shows that imprint and its recovery must be independent for each domain. In addition, switching time measurements and corresponding fitting results with the nucleation-limited-switching (NLS) model strongly indicate that imprint is caused by domain-seeds-pinning. Based on these results, we conclude that charge trapping and detrapping affecting activation barriers for domain switching, accompanied by domain switching, is responsible for imprint and its recovery.

The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects.

integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850°C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL’s grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E’ defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300°C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900°C oxide.

We correlate the concentration and configuration of electrical defects in ferroelectric Si -doped HfO 2 (FE- HfO 2 ) with the electrical device performance during wake-up and fatigue regimes. To this end, we combine time-to-breakdown (TDDB), Kelvin probe force microscopy (KPFM), conductive atomic force microcopy (C-AFM) and Scalpel SPM, probing for the first time, the nanoscopic material variations as a function of device's field cycling behavior.

The electrical performance and reliability of MOSFETs and charge-trap flash memories are influenced by the traps in the gate dielectric. Trap properties depend on the atomic structure of the dielectric and are thus expected to be affected by mechanical stress, which modifies the bonds between atoms. Consequently, the mechanical stress, either engineered or created as a side effect of fabrication, needs to be considered in order to improve the device performance and reliability. This work demonstrates a systematic and controlled experimental study of the trapping process in individual gate oxide defects under externally applied mechanical stress. The significant and reversible impact of the mechanical stress on the trapping behavior is demonstrated and a theory to explain the observations is proposed.

© 2019, Springer Science+Business Media, LLC, part of Springer Nature. Dangling bond defects (DBs) in silicon-passivated (1- or 3-nm thick Si cap) strained-(100)Si 1−x Ge x (x = 0.25–0.55) layers at interfaces with 1.8-nm thick HfO 2 gate dielectric are studied by means of Electron Spin Resonance (ESR) spectroscopy. The results suggest a dominant contribution of Si DBs (P b0 centers), a considerable fraction of which is located at the interface between the Si substrate crystal and the pseudomorphic Si 1−x Ge x film. The density of Si DBs in the Ge containing samples is significantly lower than at the reference (100)Si/ HfO 2 interface and decreases below the ESR detection limit (≈ 0.8 × 10 11 cm −2 ) with increasing thickness and Ge concentration in the Si 1−x Ge x layer. However, the beneficial effect of Ge becomes less pronounced when the thickness of the Si cap is reduced to 1 nm or in the case of direct deposition of HfO 2 on top of uncapped Si 1−x Ge x . From these observations we conclude that DBs are eliminated due to in-diffusion of Ge from the Si 1−x Ge x channel into interfacial Si layers, bringing the concentration of Ge to the range in which generation of Si DBs becomes energetically unfavourable, in agreement with previous observations on condensation-grown Si 1−x Ge x layers. ispartof: JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS vol:31 issue:1 ispartof: location:FRANCE, Strasbourg status: Published online

For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology.

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

The mechanism of imprint in FE-HfO 2 is investigated in detail. It is clearly shown that the imprint can be recovered by additional pulses and domain switching is indispensable for the recovery. The results from sub-loop measurement suggest that the imprint of each domain can be considered to be independent. Switching time measurements reveal that the imprint is well described by the nucleation limited switching kinetic model. In addition, a clear correlation between imprint and gate leakage current is successfully demonstrated. Based on these results, a model for imprint is proposed.

Voltage transient overshoot is an essential device characteristic of ESD protection diodes under CDM-like stress. Using 3D TCAD and vfTLP characterization, the impact of device architecture and middle-of-line contact scheme on voltage transient overshoot characteristics can be further explored in next bulk FinFET and GAA technology nodes.

Potential solutions for the reliability challenges of high- k metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported. A detailed study of Negative Bias Temperature Instability (NBTI)-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-k fluorination and/or cap, metal gate) is presented. The presence of Nitrogen throughout the HKMG stack can originate either from high-k processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO 2 interface region, together with AIO x (and F) incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate two strategies to tolerate the inherently large high-k defect densities: i) replacing inversion mode devices with highly doped junction-less transistors, or ii) engineering dipoles at the interface between SiO 2 and HfO 2 to suppress the carrier-defect interaction. The latter approach is demonstrated for nMOS PBTI and, for the first time here, also for pMOS NBTI, as even this aging mechanism is controlled by high-k defects in ultra-thin EOT low thermal budget gate stacks.

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

N-channel FETs with ferroelectric (FE) HfZrO gate oxide are fabricated, showing steep subthreshold slope. The hysteresis vs. subthreshold slope tradeoff, performance dependence on the bias voltage and the competition between trapping and FE behavior are reported and discussed. A transient Id-Vg measurement technique assisting in differentiating between trapping and FE behavior is introduced.

This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.

The last decade of BTI research has seen a frantic search for ultra-fast measurement methods to correctly understand the impact of fast as-grown traps which impact the initial phase (1 ks) of the degradation and recovery. These methods focus mostly on determining the time-dependence of the threshold voltage shift. Other experimental methods able to resolve the energetic distribution of traps in the bandgap have recently not been as frequently employed as they introduce a large delay and also require switching the device into accumulation, which considerably accelerates recovery. Here we use detailed CV measurements to study NBTI/PBTI in SiO 2 nMOS/pMOS capacitors. We extract a unique defect band inside the SiO 2 insulator which can describe the build-up of near-interfacial states over time in all four combinations using our recently suggested gate-sided hydrogen release model. Our results suggest that depending on the transistor type and stress bias conditions, the generated slowly-recovering near-interfacial states are due to a combination of slower oxide traps and faster P b centers.

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

We study hot carrier degradation in Si 0 . 75 Ge 0 . 25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

We perform a comprehensive analysis of hot-carrier degradation (HCD) in FinFETs. To accomplish this goal we employ our physics-based HCD model and validate it against experimental data acquired in n-FinFETs with a channel length of 28 nm. We use this verified model to study the distribution of the trap density across the fin/stack interface. The methodology is applied to analyze the effect of transistor architectural parameters, namely fin length, width, and height, on HCD. Our results show that at the same conditions HCD becomes more severe in shorter devices and in transistors with wider fins, while the impact of the fin height on the damage is weak. Finally we demonstrate that a proper HCD description can be achieved only with a physics-based model.

Display Omitted Metal-Insulator-Metal capacitors with strontium titanate and ruthenium electrodes.EOT=0.38nm @ 0V and current density 10-7Acm-2 @ ?1V and 25?C.J-V and C-V behavior modeled with defects and multi-phonon trap-assisted-tunneling.Relaxation measurement indicate charge loss of 6.5% @ 1s and 25?C. The electrical properties of Ru/SrTiOx/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38nm at 0V and current density of 10-7Acm-2 at ?1V and 25?C meet the sub-20nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.

We model the main characteristics of metal-insulator-silicon field-effect transistors (MISFETs) with different gate insulators using the carrier energy distribution function calculated with a Spherical Harmonics Expansion method. In addition to standard devices with Silicon Dioxide or Oxynitride we study a hypothetical MISFET with a rather new crystalline dielectric-Calcium Fluoride. The real physical parameters of the $$\hbox {CaF}_{2}$$ CaF 2 /Si tunnel barrier are used in our simulations. The obtained characteristics of the transistors with $$\hbox {CaF}_{2}$$ CaF 2 are, in some details, better than those of the devices with traditional oxides. Being a step forward in the context of the industrial implementation of fluorite, this work opens the possibility of simulating the characteristics of different silicon-based devices with crystalline insulators.

The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry-relevant solutions for FF and GAA-NW Si and high-mobility devices, with multiple processing options. Considerations for managing SH in future technologies are provided.

PBTI improvement in HfO2 nFETs achieved by a controlled insertion of La.Anomalous negative ΔVTH due to charge exchange between high-k and metal gate.Anomalous and conventional PBTI components are decoupled and studied separately.Analytical model including both components for lifetime extrapolation is presented. Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold VTH voltage of advance CMOS technologies. Furthermore, a reduction of the positive VTH drift (instability) has been reported for rare-earth doped nFETs under positive gate bias stress at high temperature. However, a non-optimized process can lead to an anomalous VTH behavior. We demonstrate that two independent components are responsible for this anomalous behavior which can be decoupled, individually studied, and then projected for meaningful lifetime extrapolations.

(Si)Ge channel pMOS technology offers remarkably reduced Negative Bias Temperature Instability (NBTI) at ultra-thin EOT.We ascribe this property to a reduced interaction of channel holes with dielectric defects thanks to energy decoupling.The reduced NBTI projects to a dramatic reduction of the time-dependent variability in nanoscale devices.Other device degradation mechanisms are shown not to constitute showstoppers. With a significantly reduced Negative Bias Temperature Instability (NBTI), SiGe channel pMOSFETs promise to virtually eliminate this reliability issue for ultra-thin EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. Other reliability mechanisms such as low-frequency noise, channel hot carriers, and time-dependent dielectric breakdown are shown not to be showstoppers.

The time-dependent variability of nanoscaled Si0.45 Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as 1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology.

Bias temperature instabilities (BTI) are serious reliability issues in high-k technologies and occur for positive and negative stress voltages in both n and pMOSFETs. The cases with the strongest degradation, namely negative BTI (NBTI) in pMOS and positive BTI (PBTI) in nMOSFETs, are typically studied and modeled separately, which led to considerable inconsistencies regarding the distributions of the responsible defects. Here we present the first study which successfully describes all four combinations of BTI in n/pMOSFETs within a single model. This was achieved by determining the physical properties of the defects in HfO 2 and in SiO 2 . Using our extraction method, any ambiguity regarding the location of the defect bands is completely eliminated, allowing for correct physics-based extrapolation of degradation data to use conditions.

We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al 2 O 3 , HfO 2 on InGaAs shows a minimum defect density ∼0.2eV below the channel E C . By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.

For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO 2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W NW ≤25nm, H NW ∼22nm), with increased doping enabling ION improvement without I OFF penalty for W NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V T mismatch performance shows higher A VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d NW ≥20–30nm), integrated on the same 300mm Si platform as lateral devices. Low I OFF , I G , and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

SiGe and Ge pMOSFETs, with channel passivation by Si cap and standard SiO2/HfO2 gate stack, show a very strong oxide electric field dependence of NBTI, beneficial for low voltage operation. However, standard NBTI extrapolation based on voltage accelerated stress tests is complicated for these devices due to an apparent correlation of time-dependence exponent (n) to the applied gate stress overdrive voltage (VOV). This behavior is found to be unrelated to the measurement delay, but induced by a gradual reduction of the stress oxide electric field during the NBTI stress due to the buildup of threshold voltage shift. A unique analog circuit based test setup is proposed to perform a quasi-constant oxide field BTI stress. This method eliminates the field reduction effect during NBTI stress and therefore decouples the time exponent from the applied stress VOV. This allows to calculate the time-to-failure for SiGe and Ge channel devices unambiguously, confirming the superior NBTI reliability of these pMOS technologies as compared to standard Si devices. Possible limitations of the proposed measurement method are also discussed.

It is commonly accepted that the susceptibility of conventional Si channel pMOSFETs to the negative bias temperature instability (NBTI) is a serious threat to further scaling. One possible solution of this problem is the use of SiGe quantum-well devices, which not only offer high mobilities but also superior NBTI reliability compared to conventional silicon transistors. It has been speculated that the latter is due to the energetically higher valence band edge of the SiGe channel with respect to Si, which increases the energetic separation between the defect bands in the high-k gate stack and the channel. We investigate this claim by comparing the behavior of single-defects in nanoscale devices to the averaged behavior of the large number of defects visible in large-area devices. Using detailed TCAD simulations together with the four-state non-radiative multiphonon model we determine the energetic and spatial locations of the traps in the gate stack and confirm that the previously developed picture correctly explains the significant reliability benefits of SiGe channel devices.

We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Hot carrier (HC) reliability is investigated at ‘on’ and ‘off’ state stress conditions in junctionless (JL) gate-all-around HK/MG nanowires. We discuss the reason of improved HC reliability in JL nanowire compared to the inversion-mode (IM) nanowire at ‘on’ state stress condition. Then we present the impact of ‘off’ state stress in the JL nanowire, considering that a high gate oxide field is applied at the ‘off’ state. Additionally, the improved sub-threshold swing (SS) after HC stress in some JL nanowires is discussed.

A comparative study of the growth behavior of nm-thin ruthenium layers by plasma enhanced atomic layer deposition using two ruthenium precursors is discussed. For bis(ethylcyclopentadienyl)-ruthenium or Ru(EtCp)2, we have found a large incubation time on titanium nitride when using N2/NH3 plasma. With N2/H2 plasma the incubation was significantly reduced. For (methylcyclopentadienyl-pyrrolyl)ruthenium or MCPRu, no incubation was observed for either plasmas. The measured growth per cycle was ~ 0.02 nm for Ru(EtCp)2 whereas ~ 0.04 nm for MCPRu. The top surface of the PE-ALD Ru films can be oxidized without surface roughening by applying a low pressure O2 anneal, while O3 exposure leads to roughening due to etching and re-deposition downstream of etched Ru. Awareness of the impact of oxidizing ambients on Ru is essential for successful integration of Ru layers as electrode in metal-insulator-metal capacitors.

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.

The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 μs, which would be missed if the CCP were used.

Introduction of high-k dielectrics in Flash memory is seen as a must for the upcoming technology nodes. Hafnium aluminate (HfAlO) has been identified as a possible candidate for implementing the interpoly dielectric in floating gate memory. In this work, we establish a link between the material morphology and its electrical response, allowing to understand memory device behavior and to consequently assess the potential and limitations of HfAlO as IPD in a memory cell.

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.

A pulsed Q-V method enabling charge or capacitance measurements versus gate voltage of aggressively scaled, leaky (up to ~10 A/cm2 ), and charge-trapping high-kappa MOS devices is introduced. The method does not require RF structures and can be used on MOS capacitors or MOSFETs with an oxide capacitance of 1-10 pF. The method enables the measurement of charge trapping characteristics in leaky MOS devices and allows the accurate measurement of the inversion charge without influence of trapping for the determination of mobility in leaky charge-trapping MOS devices

Reliability issues of MOSFETs such as bias temperature instability (BTI), random telegraph noise (RTN), and stress-induced leakage current (SILC), are linked to the trapping of charges in oxides. Even though the chemical structure of these oxide defects is still the subject of debate, detailed studies of these reliability phenomena have shown that their physical behavior can be successfully described by non-radiative multi-phonon (NMP) theory. In this work we characterize and study a pMOS high-k FinFET technology starting from degradation measurements up to the simulation of the energy barriers in the framework of NMP theory. This allows to investigate the aforementioned reliability issues all based on their common cause, the microscopic oxide defects.

Stochastic device degradation — due to individual oxide defects — like Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI) causes a threshold voltage drift of transistors resulting in decreased SRAM yield and performance. BTI and RTN has been shown to follow an defect-centric behavior, which can be bimodal in nature for heterogeneous gate oxide stacks. Consequently the tail of the distribution can significantly deviate from a Gaussian distribution. In this paper we combine statistical silicon extracted from large transistor arrays (32k) designed and fabricated in an advanced 20nm High-k/Metal Gate process, with current state-of-the-art statistical assessment techniques in order to acquire a realistic impact of BTI degradation on the yield and performance of 6T SRAM cells.

Based on physically-extended methodology, measurements and simulations show that implementing high-mobility materials and particularly alloys, such as a SiGe buffer for mobility enhancement in a Ge channel, can result in a 115% increase in self heating in the N7 node, compared to standard Si FinFETs.

We present a comprehensive study of ESD reliability (TLP) on planar nMOSFETs with In 0.53 Ga 0.47 As as the channel material. Two types of traps are found during ESD stress. They are formed through independent mechanisms: transient Ef-lowering induced pre-existing e-traps discharging in the gate stack and hot hole induced e-traps generation through impact ionization in the InP buffer. These two types of traps explain the observed walk-out of off-state channel leakage current as well as the two-stage current conduction phenomena in the TLP measurement. The generated e-traps are permanent and can introduce detrimental conduction current harmful to the device performance. By properly selecting the buffer material, these defects can be removed.

Here we show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced High-k/Metal Gate (HK/MG) technology, thus allowing us to fully characterize the underlying technology. BTI is shown to follow a bimodal defect-centric behavior, for NBTI related to Interface Layer (IL)(SiO 2 ) and HK trapping and for PBTI related to HK and IL/HK interface trapping. Moreover for the first time, an analytical description of the bimodal total ΔV TH shift is derived, as a special case of the generalized defect-centric distribution, which we derive in this work to accurately describe the tail of the distribution.