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A 1.2-Mpixel indirect time-of-flight (ToF) CMOS image sensor is presented to lower peak current and to cancel out multi-user interference. The proposed 4-tap 3.5- $\mu \text{m}$ demodulation pixel is optimally designed to improve quantum efficiency (QE) and demodulation contrast (DC). A new “multiple-interleaving” scheme is proposed to reduce the peak current and self-compensate fixed-pattern phase noise (FPPN) with the minimal side effect of DC imbalance. To cancel out interference from the other ToF sensors, a multi-user interference cancellation (MUIC) scheme based on pseudorandom modulation is adopted. From the measurement results, we achieve a high QE of 38% at 940 nm and a high DC of 96% and 80% at 100- and 200-MHz modulation frequencies, respectively. With the superior pixel performance, the depth noise of $\times $ 2 binning modes, respectively. The multiple-interleaving scheme suppresses the peak current to less than 0.9 A and removes the column FPPN with constant DC for the whole pixel array. The proposed MUIC proves that at least two interferers can be successfully rejected. The sensor chip is fabricated in a two-stack process with 65 nm for the top die and 65 nm for the bottom die.

CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.

We report a spectrum-sliced amplified spontaneous emission-injected wide-band gain laser covering a temperature range over 110/spl deg/C as well as entire 32 100-GHz-spaced channels (1533-1558 nm) in 155-Mb/s upstream transmissions over 25 km of single-mode fiber in a wavelength-division-multiplexed passive optical network. The wide-band gain laser diode employs asymmetric multiple quantum-well structure and low antireflection coating in order to widen the gain spectrum.

Using the W damascene process in the pixel area, M1Top pixel structure was developed. Because the M1Top pixel structure does not use the metal2 layer in the pixel block, total stack height becomes much thinner than normal pixels. From this new structure, sensitivity and QE in 1.75um pixels have been improved by 50% from that of normal M2Top pixels in 0.11um CIS process.

A WDM-PON with 50-GHz channel spacing employing RSOA-based spectrum sliced sources is presented. Colorless operations over 32 DWDM channels are demonstrated from -10 to 80 °C in 155-Mb/s transmissions over 10 km.

We report a spectrum-sliced amplified spontaneous emission (ASE)-injected wideband gain laser covering entire C-hand wavelength channels with temperature range from -30 to 80 /spl deg/C in 155 Mb/s upstream transmissions over 25 km of single mode fiber in a wavelength division multiplexed-passive optical networks (WDM-PON).