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Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SSth of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance Gm at 5.5 K. [ABSTRACT FROM AUTHOR]

In this article, vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top–down approach are demonstrated. Thanks to optimized dry etching and digital etching, high-performance Ge GAA nanowire pFETs show low subthreshold swing (SS) of 66 mV/dec, small DIBL, and ION/IOFF ratio of > 106. The impact of nanowire diameter scaling from 65 to 20 nm on the key electrical figures of merit (FOMs) of vertical nanowire devices is investigated. The devices with 65-nm diameters show the highest ION and peak transconductance Gmax due to reduced total resistance Rtot, while the smallest diameter devices yield the largest ION/IOFF ratios and the smallest DIBL due to strong gate electrostatics. The source/–drain asymmetry inherently exists in the vertical nanowire architectures. By swapping the source and drain, electrical FOMs keep the similar trend in diameter scaling. ION, Rtot, and Gmax asymmetry can be attributed to top–bottom contact resistance difference resulting from the doping deactivation effect in small nanowires. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$. The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$. Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance. [ABSTRACT FROM AUTHOR]

Abstract: Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along <110> and <100> crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 1011 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for <110> channel direction devices compared to <100> devices. The <100>n-MOSFETs showed a 45% increased electron mobility compared to <110> devices. The comparison of strained and unstrained n-MOSFETs along <110> and <100> clearly demonstrates improved electron mobilities for strained channels of both channel orientations. [Copyright &y& Elsevier]

This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device's Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc.). For model verification, it is compared to measurements performed on nanowire Schottky barrier transistors at a temperature of 5.5 K. [ABSTRACT FROM AUTHOR]

We present experimental data on analog device performance of p-type planar- and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs) as well as on n-type Tri-Gate-TFETs. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameters of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-currents up to 23 μA/μm at a gate overdrive of V gt = V d = −1 V were achieved for the GAA NW-pTFETs. Furthermore, a good output current-saturation is observed leading to high intrinsic gain up to 217. The Tri-Gate nTFETs beat the fundamental MOSFET limit for the subthreshold slope of 60 mV/dec and by that also reach extremely high transconductance efficiencies up to 82 V −1 . [ABSTRACT FROM AUTHOR]