Semiconductor nanowires (NWs) have attracted significant interest recently due to quantum size effects and novel properties that they will bring to a wide range of electronic and optoelectronic devices, chemical and biological sensors, and photovoltaics. Among the broad range of materials from which NWs can be synthesized, group IV semiconductor (Si, Ge) NWs and NW heterostructures are distinct as they promise materials compatibility and facile integration with conventional Si-based circuits. This promise has stimulated extensive efforts in developing reliable synthesis routes that yield bulk quantities of high-quality group IV NW material, including laser ablation, chemical vapor deposition (CVD) from different precursors and catalysts, chemical vapor transport reactions, and low-temperature solution-phase synthesis. Ge offers a number of properties that are superior to those of Si in device applications, for example, higher carrier mobility and larger exciton radius, and hence stronger quantum confinement in a NW, and the prospect of lower processing temperatures and thus easier integration with conventional devices. However, in contrast to Si, which forms a stable oxide with an electronically benign Si/SiO2 interface, Ge forms oxides with poor chemical stability and unfavorable electrical properties. After exposure to air, Ge NWs invariably exhibit surface oxides with thicknesses of about 2–4 nm, a significant fraction of the NW diameter. Methods to inhibit or control surface oxidation, achieve chemical stability under ambient conditions, and thus prevent uncontrolled changes of the electronic properties due to oxidation, will be an important part of any future Ge NW-based device technology. First efforts to address this fundamental issue have been initiated only recently. Layered materials, such as graphite, MoS2, or BN, in which two-dimensional sheets with complete internal bonding (i.e., no dangling bonds) are joined by van der Waals forces, are chemically inert and could be used to prevent oxidation if assembled as a protective shell around individual Ge NWs. In addition to providing an oxidation barrier, the encapsulation of the semiconductor NWs in a graphitic carbon shell would have the benefit of an already comprehensive understanding of the chemical functionalization of C surfaces, which may open up new avenues for sensing applications based on Ge/C core/shell NWs. In the presence of sufficient C, nanoparticles of some metals (Au, Pb, Sn, Fe, Ni, Co, Cu, Ti) are readily encapsulated in graphitic C shells, as metal surfaces appear to catalyze and template the assembly of ordered C sheets. Surface chemistry and reactivity of most semiconductors, on the other hand, preclude the growth of ordered C sheets, both due to the absence of catalytic effects found for metals and because of the formation of stable carbide compounds. Here, we use in situ transmission electron microscopy (TEM) experiments to demonstrate the controlled encapsulation of Ge wires in C shells at moderate temperatures. Traces of Au at the NW surface, originating from the Au/Ge catalyst particle used for growing high-aspect-ratio wires, are shown to be critical to the assembly of fragments of graphene C sheets, which then transform into well-defined multilayer shells that completely encapsulate the Ge NWs. Examination of the encapsulated wires after prolonged exposure to ambient conditions shows that the C shells remain intact and unchanged, and provide an efficient oxidation barrier for the Ge wires. Our variable-temperature in situ experiments are carried out in the temperature range between room temperature and 400 °C on C-supported Ge NWs synthesized prior to the in situ studies using CVD. Figure 1 shows TEM images of the structure and morphology of Ge NWs, obtained at room temperature prior to our in situ experiment; these images are representative of the as-grown starting material in our study. The inset of Figure 1a shows an overview of a group of wires dispersed on the C film of the TEM grid. Our method of NW dispersal creates Ge wire segments severed from the Si substrate, comprising the wire shaft as well as the tip with the residual Au/Ge catalyst particle. The slightly tapered NWs have a typical diameter of 10–50 nm at the tip, 100–200 nm at the base, and are several micrometers long. The wires have monocrystalline cores and well-defined faceted surfaces, and all exhibit a 1–4 nm thick oxide shell, as would be expected after transfer through ambient air. The TEM images of Figure 1a–c show the detailed structure close to the NW tip for one of the wires from the inset. For all NWs the Au/Ge nanoparticle at the tip shows darker contrast than the Ge wire. In high-resolution TEM images (Fig. 1b and c) the (111) lattice planes of the Au/Ge alloy with separation (0.219 nm) close to the lattice spacing of Au are clearly resolved. The NW axis is aligned with the [111] direction. The high-resolution images show lattice fringes with separation of 0.327 nm perpendicular to the C O M M U N IC A IO N S