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This paper presents a 2.5D integrated microprocessor die, memory die, and accelerator die with 2.5D silicon interposer I/Os. The use of such 2.5D silicon interposer I/Os provide a scalable interconnection for core-core (up to 32 cores), core-memory ( $4\times $ storage capacity) and core-accelerator ( $4.4\times $ speedup in H.264 decoder). The 2.5D integrated chip was implemented in GF 65 nm process with multicore microprocessor operated at 500 MHz under 1.2 V supply with 1.08 W power dissipation. A pair of 8 Gbps 2.5D silicon interposer I/O is designed for each of 12 inter-die communication channels, achieving a bandwidth of 24 GBps with 7.5 pJ/bit energy efficiency. As a result, the specified applications such as H.264 video data analytics and AES encryption can achieve significant performance improvement of throughput and energy efficiency. [ABSTRACT FROM AUTHOR]

A domain specific multicore processor for public-key cryptography is proposed in this paper. This processor provides flexible and efficient computation for various forms of RSA and ECC algorithms, fulfilling low-latency or high-throughput requirements of different application scenarios. By using a heterogeneous multicore architecture, the proposed processor enables high speed parallel implementations of kernel arithmetics of public-key algorithms. A long-word-length modular multiplication can be partitioned into parallel tasks executed by the high performance multipliers distributed in multiple cores. Some dedicated communication mechanisms minimize inter-core data transferring latencies of the processor. The proposed processor is implemented under TSMC 65 nm LP CMOS technology. Experimental results show that our design outperforms previous works based on varied platforms in performance, for instance, it can complete a 1024-bit RSA encryption in 0.087 ms at 960 MHz. Moreover, we also study the area reduction techniques for proposed multicore processor from the perspectives of algorithm, architecture, and circuit. [ABSTRACT FROM AUTHOR]

A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 \times 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm^2 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator. [ABSTRACT FROM AUTHOR]