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Hauppauge, N.Y. - In one stroke last week, Standard Microsystems Corp. (SMC), notable in the personal-computer industry primarily for its Super I/O chips, acquired a core-logic business, the most innovative […]

San Francisco - Hewlett-Packard Co. unveiled the next step in its PA-RISC family, and attendees viewed internals of Digital Equipment's Alpha 21164 and Hal R1 RISC CPU designs for the […]

San Francisco -- The Intel P6 CPU may grab the headlines when the doors open this week on the International Solid-State Circuits Conference, but the 200-iSPEC microprocessor is just one […]

Santa Clara, Calif. -- With a new year and new concerns, the media circus surrounding the floating-point bug in Intel Corp.'s Pentium CPUs is subsiding. But the aftereffects of the […]

Washington -- The Federal Trade Commission will require multiple production sources for Digital Equipment Corp.'s Alpha microprocessor technology as part of a settlement last week that clears the way for […]

On Nov. 7, 1994, EE Times was the first newspaper to report the existence of the now-infamous bug in the Pentium microprocessor. Intel's response-and the aftermath-will be studied by business […]

Mountain View, Calif. - Continuing the specialization that has become a recent characteristic of the MIPS CPU family, NEC Corp. today will unveil a new 64-bit MIPS microprocessor aimed at […]

Irvine, Calif. -- Even in the absence of a clear volume market, the mini-RISC-processor architectural battles are escalating toward all-out war. Entrenched mini-RISC players are refining their designs and moving […]

The article focuses on the problems of benchmarking embedded systems. Benchmarking embedded systems has always been difficult. As those simple MPUs of yore have evolved into complex, multitasking systems-on-chip (SoC), often with hardware accelerators, shared on-chip memory structures and buses, and intelligent peripherals, the simple question of whether a given chip can do the job has become a huge issue. The Embedded Microprocessor Benchmark Consortium is taking on these challenges. With three major initiatives, the group hopes to create new, open and licensable benchmarks that will be predictive for the multicore SoCs and sophisticated applications that characterize the current market. The three primary areas for benchmarking, namely, automotive control, multicore SoCs and storage controllers.

Focuses on the controversy behind the decision of Intel Corp. to take the hydra-headed designs known as multicore processors into the volume realm. Declaration of Paul Otellini, Intel president, on the microprocessors; Software cost; New features.

Reports on Chip Designs Ltd.'s launch of a massively parallel array of heterogeneous processors that it believes will jettison digital signal processing, field programmable gate arrays and application-specific integrated circuit incumbents from the third-generation basestation designs. Processing capabilities; Tools and development environment; Potential applications.

Discusses the evolution of system-on-chip designs in the field of electronic engineering. Background on component-based design; Arrival of the microprocessor; Overview of the register-transfer level approach to implementing design requirements.

Focuses on processor designers' increase of the number of instructions per cycle of microprocessors to enhance performance. Design and renaming issues; Technical challenges; Success factors; Benefits and applications.

Reports on the exhibition of microprocessors at the Hot Chips '93 conference in Palo Alto, California, in August 1993. Processors for the mobile-computing market; Adaptations of different architectures.

Introduces IBM Corp.'s Blue Lightning family of microprocessors. Challenge to Intel Corp.'s 486 family; Speed; Expanded external bus; License agreement with Intel; Expected shipment date; Shortage in 486 chips; Success of IBM's processors in Taiwan;.

Presents a revisionist look into the history of microprocessor architectures. Intel Corp.'s 1969 design project for calculator manufacturer Busicom; Four-Phase Systems' introduction of the AL1 chip which adapted the IBM System 360 architecture to the problems of controlling an intelligent terminal; Synthesis between seminal architectures and a specific application need.

Focuses on Intel Corporation's PentiumPro which was formerly known as P6. Improvements to system; Comments from product manager Robert Colwell; How project delays effect Intel's strategy.

The article elaborates on the development of and present trends on central processing units (CPU) in field-programmable gate arrays (FPGA). A discussion on the various attempts to adapt CPU cores in an FPGA fabric, which includes the ColdFire microprocessor by Freescale Semiconductor and the ARM7 processor family from ARM Ltd., and the difficulties encountered is presented. The various approaches of Altera Corp., Xilinx, Inc., Actel Corp., and Lattice Semiconductor Corp. in developing CPU cores and the capabilities of these cores are discussed.

The article examines problems faced by a systems on a chip (SOC) team in integrating high-speed serial input/output (I/O) blocks. The potential of high-speed serial I/O as an alternative to the wide parallel buses that were common on processor chips and SOC has been observed by system designers. Among the challenges faced by an SOC team is the physical interface. According to Hemant Shah of Cadence, the only means one may feel good about his intellectual property (IP) selection is to model the block in the board environment where the chip will be used.

The article offers information on virtualization. A system is virtualized when it has undergone three steps: when a boundary has isolated the system from its environment, when designers have identified the inputs and outputs that cross the boundary along with the transforms that produce the outputs and when designers are able to produce a functionally equivalent block or one that accepts the same inputs and produces the same outputs under the same circumstances within an electronic system. Virtualization is expected to unleash a revolution as great as that of the microprocessor in the future.

This article highlights the growing skepticism among microprocessors designers about the future of system on chip (SOC) technology. SOC is the technology being used for tool integration in microprocessor design and development. The advance of SOC technology is made by vacuuming up all the digital functions in a system until there is nothing of important cost or function left outside the microprocessor. Technology forecasters have identified precision analog or radio frequency (RF) blocks as the next frontier for SOC integration. Manufacturers of cellular-phone handsets, such as Infineon and Texas Instruments, are already exploring RF blocks for SOC integration.

The article reports that ARM Ltd. raised few eyebrows with the long-anticipated announcement of its Cortex A8 CPU core a couple of weeks ago. Indeed, at least two other chip makers, PMC-Sierra and Intrinsity, have implemented discrete MIPS microprocessors operating in the 1-GHz range, and at least one system-on-chip vendor, Raza Microelectronics, has pushed a 90-nanometer internally developed embedded MIPS core to 1.5 GHz for high-performance networking. The Cortex A8 design has been architected with the assumption that it will be implemented using ARM's dynamic voltage island technology, an approach that is just being supported in the necessary Artisan libraries and that is still a generation away for mainstream electronic design automation tools.

Discusses the use of predicting the performance of a processor in a real application. Reference to the organizations who have introduced suites of tasks derived from actual application code; Information on the Embedded Microprocessor Benchmark; Details of benchmarking challenges.