Search

In this paper, for the first time, a dual-metal double-gate with oxide stack (low-k/high-k) junctionless MOSFET (DM-DG-OS JL-MOSFET) based sensor device has been explored for finding its suitability in detecting charged nanometric biospecies under dry environment condition. The analysis of sensing performance of the device for such detection is made in terms of the absolute and the relative changes in threshold voltage (Vth). The influence of work-function difference of dual metal gate electrodes, along with the position of nanogap cavity, on the sensing metrics has been thoroughly investigated. The impact of the cavity dimensions on sensitivity parameters of the projected device is also studied. An optimum cavity dimension, for channel length (Lch) of 1 µm, is found to be 400 nm × 10 nm in yielding measurable sensitivity parameters for charged nanometric biospecies detection. A device with 1-µm Lch exhibits superior sensitivity performance in terms of percentage improvements in the absolute and the relative changes in Vth for a higher drain-side gate-metal work-function (ϕM2) relative to source-side gate-metal work-function (ϕM1) for source-side cavity (400 nm × 10 nm) compared to the case when ϕM1>ϕM2 and the cavity is located near drain-side. Respective performance enhancements are found to be 30.7% and 74% for detection of negatively charged nanometric biospecies. The sensor devices with Lch of 50 nm show the similar trend. [ABSTRACT FROM AUTHOR]

This paper reports unique InGaAs-based ion-sensitive field-effect transistor (ISFET) sensor devices having a sensing gate in addition to the traditional floating gate with different kinds of barrier materials such as no barrier, single barrier (InP) and double barrier (InP and InAlAs), at sub-100 nm technology node. The impact of barrier layers coupled with the modified gate architecture on the sensing performance of the proposed devices has been investigated and compared thoroughly in terms of different performance metrics, e.g., threshold voltage sensitivity, ON-current sensitivity, and ON/OFF-current sensitivity. Interestingly, it has been found that the sensor device with a single barrier exhibits the highest threshold voltage sensitivity of ~ 67 mV/pH and largest ION/IOFF ratio sensitivity of 25/pH, compared to the other devices. Furthermore, it is worth mentioning that the threshold voltage sensitivity of the single-barrier sensor device crosses the conventional Nernst limit of 59 mV/pH at room temperature, by 14%. Critically analyzing the results, it is found that the sensor device with a single barrier has evolved as the most promising device for pH-sensing application, not only from the standpoint of high sensitivity parameters, but also from the fabrication point of view. [ABSTRACT FROM AUTHOR]

We investigate the logic performance of hybrid (H) CMOS devices comprising Ge p-MOSFETs and Si n-MOSFETs in terms of rise time, fall time, propagation delay and noise margins using extensive numerical device simulation. We analyse CMOS devices featuring channel thickness (T ch ) ranging 5–10 nm, spacer length (L sp ) from 1 to 10 nm at channel length (L g ) of both 20 and 30 nm. Our investigation reveals that hybrid CMOS inverters exhibit reduction in rise time and propagation delay by 53.5% and 31.6% as compared with the corresponding Si value, respectively for the ratio of widths of p- and n-MOSFETs (r) = 3, T ch = 7 nm and L sp = 5 nm at L g = 20 nm. Furthermore, the frequency of oscillations of a 3-stage ring oscillator constructed with hybrid CMOSFETs shows a significant improvement of 151.7% at L g = 20 nm for r = 1, over its equivalent Si counterpart. [ABSTRACT FROM AUTHOR]

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( Lg ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance gm , transconductance generation factor, and voltage gain Av exhibit significant improvement when a spacer of high dielectric constant k , such as 25, and small length L_{\textrm {sp}} , such as 5 nm, are used for both L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower k$ and larger L_{\textrm {sp}} of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes. [ABSTRACT FROM AUTHOR]

A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices. [ABSTRACT FROM AUTHOR]

MOSFETs with InGaAs in the channel show great promise for high-performance digital applications owing to enhanced electron mobility. In this letter, the analog performance is reported for the first time for an inversion-type enhancement-mode InGaAs-channel MOSFET. With the help of a device simulator, the device parameters for analog applications such as transconductance (gm), transconductance-to-drain-current ratio (gm/ID), drain resistance (RO), intrinsic gain, and unity-gain cutoff frequency (fT) are studied for such a device and compared with those for a similarly sized MOSFET. Our results show that InGaAs devices outperform their Si counterparts for analog applications. [ABSTRACT FROM AUTHOR]