Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs.

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( Lg ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance gm , transconductance generation factor, and voltage gain Av exhibit significant improvement when a spacer of high dielectric constant k , such as 25, and small length L_{\textrm {sp}} , such as 5 nm, are used for both L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower k$ and larger L_{\textrm {sp}} of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes. [ABSTRACT FROM AUTHOR]