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In this paper, we report the fabrication and characterization of Lg = 50 nm Gate-All-Around (GAA) In0.53Ga0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated GAA In0.53Ga0.47As NS MOSFETs feature a bi-layer high-k dielectric layer of Al2O3/HfO2, together with an ALD-grown TiN metal-gate in a cross-coupled manner. The device with Lg = 50 nm, WNS = 200 nm and tNS = 10 nm exhibited an excellent combination of subthreshold-swing behavior (S < 80 mV/dec.) and carrier transport properties (gm_max = 1.86 mS/μm and ION = 0.4 mA/μm) at VDS = 0.5 V. To the best of our knowledge, this is the first demonstration of InxGa1-xAs GAA NS MOSFETs that would be directly applicable for their use in future multi-bridged channel (MBC) devices. [ABSTRACT FROM AUTHOR]

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance. [ABSTRACT FROM AUTHOR]

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering. [ABSTRACT FROM AUTHOR]

In this paper, we aim to decompose gate capacitance components in InGaAs/InAlAs quantum-well (QW) metal-oxide-semiconductor field-effect-transistors (MOSFETs), in an effort to physically investigate their gate capacitance (Cg). First, we verified their validity with 1-D simulation and experimental Cg data in various types of InGaAs/InAlAs QW MOSFETs with different channel thickness (tch). Both quantum capacitance (CQ) and centroid capacitance (Ccent) were highly relevant to total gate capacitance (Cg) of the InGaAs/InAlAs QW MOSFETs. Second, the total Cg did not saturate at a strong inversion regime. This is a consequence of the second subband inversion layer capacitance (Cinv_2) and, more importantly, its increase with VG. Lastly, we studied the role of channel thickness (tch) scaling, which helps to increase the total gate capacitance by enhancing both CQ and Ccent. [ABSTRACT FROM AUTHOR]

The radiation hardness of AlGaN/GaN high-electron-mobility transistors (HEMTs) is found to improve with increasing GaN channel thickness. Epitaxial MgCaO shows promise as a radiation-tolerant gate dielectric, with only small shifts in operating parameters of metal–oxide–semiconductor HEMTs observed at doses up to 1 Mrad(SiO2). Bias-induced electron trapping and radiation-induced-hole trapping can occur in the MgCaO, depending on the applied bias during stress and/or irradiation. AC transconductance measurements are used to help understand charge trapping in these devices. [ABSTRACT FROM PUBLISHER]

In this letter, we have investigated the properties of In0.53Ga0.47As quantum-well (QW) metal–oxide–semiconductor field-effect-transistors (MOSFETs) on a 300-mm(100) Si wafer. We have explored the impact of scaling down In0.53Ga0.47As channel thickness ( \textt\mathrm {ch}) from 15 to 5 nm. The fabricated devices show excellent electrostatic integrity, such as subthreshold-swing (SS) < 80 mV/decade and drain-induced barrier-lower (DIBL) <20 mV/V. Furthermore, we have extracted the effective mobility ( \mu \textit {n\_{}$eff}}) of the fabricated devices to investigate the carrier transport properties of the InGaAs MOSFETs with different values of \textt\mathrm {ch} . The device with \textt\mathrm {ch} = 15 nm displayed a value of \mu \textit {n\_{}$eff}} = 2,190$ cm2/V-s at room temperature. This valuewas found to decrease as \text{t}_{\mathrm {ch}} was scaled down. [ABSTRACT FROM PUBLISHER]

Conventional methods to extract an effective mobility ( \mu \mathrm {eff} ) in a metal–oxide–semiconductor field-effect-transistor (MOSFET) tend to ignore the portions of parasitic components of the device. This can cause a substantial error in the extracted value of the effective mobility. In this letter, we have proposed a unified procedure that enables to accurately capture each portion of parasitic series resistance ( $R_{{\mathrm {SD}}} ) and parasitic gate capacitance ( Cg\{\mathrm {par}} ) components. Then, we have investigated the impact of the parasitic components on the extracted value of the effective mobility in a gate-last surface-channel In0.7Ga0.3As quantum-well MOSFET. We have found that the extracted effective mobility using our method turns out to be independent upon gate length ( L{\mathrm {g}} ) from 10 to 4~\mu \textm , which verifies the accuracy of the approach proposed in this letter. [ABSTRACT FROM PUBLISHER]

High-quality \SiO2 is deposited on GaN by radio frequency (RF) magnetron sputtering at room temperature. Adding oxygen to the sputtering gas effectively compensated for the oxygen vacancies and resulted in a breakdown field of 9.6 MV/cm for the sputtered- \SiO2 film on GaN. The reduced electron concentration and mobility of the 2-D electron gas due to the sputtering-induced surface damage were effectively removed by an optimized postannealing treatment. A sputtered-\SiO2\/ \AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistor (HEMT) (MOSHEMT) was demonstrated with the lowest thermal energy requirement among all the dielectric deposition techniques, which exhibited a saturation drain current of 621 mA/mm and a breakdown voltage of 205 V at the gate–drain distance of 2 \mu\m. More than four orders of magnitude lower gate leakage current than conventional HEMT of the same dimension was achieved. These characteristics demonstrate excellent potential of using RF magnetron sputtering to produce gate insulators for GaN-based MOSHEMTs. [ABSTRACT FROM PUBLISHER]

We have fabricated and investigated several types of MOSFETs with normally-off operation. The recessed-gate MOSFET is preferred for normally-off operation, because the threshold voltage (Vth) of the device can be easily controlled, but it suffers from relatively modest current drivability which must be improved by adopting appropriate device structure and/or process. Enhanced performances have been achieved in this work by combining the recessed-gate technology with additional processes, such as: the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, the post-deposition annealing of gate oxide to decrease the gate leakage current, the re-growth of n+ layer for source/drain to improve the access resistance and Vth uniformity, the stress control technology to achieve extremely high 2-D electron-gas density (2DEG) on source/drain and decrease the series resistance, and the use of the p- back-barrier to decrease the buffer leakage current. The -based FinFET with very narrow fin was also investigated as a possible candidate for high performance normally-off MOSFETs. [ABSTRACT FROM AUTHOR]

We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal directions was investigated for different channel geometries. The biasing condition which enables the simultaneous activation of all channels and gives rise to volume inversion is discussed. [ABSTRACT FROM AUTHOR]

Normally off Al2O3/GaN MOSFETs are fabricated with a tetramethylammonium hydroxide (TMAH) treatment as a postgate recess etch. The effects of the surface treatment on the etched GaN surface are investigated using low-frequency (1/ f ) noise and capacitance–voltage ( C – V ) measurements. For a quantitative comparison with conventional devices, the oxide trap density ( ) is extracted using the unified 1/ f noise model, whereas the interface trap density ( D\mathbf {it} ) is extracted using the high–low-frequency C – V method. After the TMAH treatment, N_{\mathbf {ot}} is found to have decreased from 5.40 \times 10^{\mathrm {\mathbf {19}}} to 2.50 \times 10^\mathrm \mathbf 19~\mathrmeV^\mathrm \mathbf -1 \mathrmcm^\mathrm \mathbf -3 , whereas D\mathbf {it}^{\vphantom {(}} is decreased from 2.8 \times 10^\mathrm \mathbf 12 to 1.1 \times 10^\mathrm \mathbf 11~\mathrmeV^\mathrm \mathbf -1 \mathrmcm^\mathrm \mathbf -2 , as compared with conventional devices. The surface treatment is thus shown to lower trap density in the Al2O3/GaN MOSFETs by smoothing the surface and suppressing plasma damage in the recessed GaN surfaces. [ABSTRACT FROM AUTHOR]

A crack-free AlGaN/GaN heterostrucure is grown on 4-in Si (111) substrate with AlSiC precoverage layer. Covering the Si surface with the AlSiC layer, until the growth of the AlN wetting buffer layer, is found to be effective in compensating the strong tensile stress in the GaN layer grown on Si substrate. The metal-oxide-semiconductor field-effect transistor, fabricated on this AlGaN/GaN heterostructure, exhibits excellent normally-off characteristics with threshold voltage of 7.2 V, maximum drain current of 120 mA/mm, ON/OFF current ratio of \sim10^8, and subthreshold slope of 80 mV/decade. [ABSTRACT FROM PUBLISHER]

Heavily doped GaN nanochannel fin-shaped field-effect transistors (FinFETs) without heterojunction have been fabricated and characterized for the first time. Simplified pragmatical technology for GaN epitaxial growth and FinFET process was used to achieve nanodevices with a channel width from 40 to 100 nm and a gate length of 1 \mu\m. They exhibit excellent on-state performance, such as maximum drain current of 670 mA/mm and maximum transconductance of 168 mS/mm. Record off-state performance was measured: extremely low leakage current of \sim\!\!\10^-11\ \mA and source–drain breakdown voltage of \sim280 V. The subthreshold slope of 68 mV/decade is close to the theoretical limit (60 mV/decade, so far achieved only in SOI MOSFETs) and leads to very high Ion/Ioff ratio of \10^8 - \10^9. The proposed heterojunction-free nanochannel GaN FinFET is a very promising candidate not only for high-performance and high-speed integrated circuits but also for high-power applications. [ABSTRACT FROM PUBLISHER]

A high-performance normally off GaN-based MOSFET was fabricated. The buffer layer of the MOSFET was grown by varying the growth temperature to control the size of nucleation sites which results in an extremely high buffer resistance (> \10^12\ \Omega/\sq). The fabricated small-area MOSFET exhibited excellent normally off device characteristics, such as a threshold voltage of 2 V, maximum drain current of 253 mA/mm, on–off current ratio of \5.5 \times \10^7, destructive breakdown voltage of 830 V, and leakage current of 0.7 \mu\A/mm at a VDS of 600 V. The corresponding values of the large-area MOSFET with a multifinger pattern were 0.6 V, 6 A, \1.3 \times \10^7, 670 V, and 50 \mu\A (0.28 \mu \A/mm). [ABSTRACT FROM AUTHOR]

Normally off \Al2\O3\/\GaN MOSFETs are fabricated by utilizing a simple tetramethylammonium hydroxide (TMAH) treatment as a postgate-recess process. The TMAH-treated device with a gate length of 2.5 \mu\m exhibited excellent device performances, such as a threshold voltage of 3.5 V, a maximum drain current of 336 mA/mm, and a breakdown voltage of 725 V, along with extremely small gate leakage current of about \10^-9\ \A/mm at Vgs = \15\ \V, which is approximately six orders lower in magnitude compared to that of the device without TMAH treatment. [ABSTRACT FROM AUTHOR]

AlGaN/GaN metal-insulator-semiconductor field-effect transistors with fin structures (AlGaN/GaN MIS-FinFETs) were fabricated and characterized by changing fin width and using different dielectric layers. The FinFET with 20 nm-thick SiO2 dielectric layer exhibits a very small subthreshold swing (SS) of 56 mV/decade. However, the threshold voltage of the device is too low to ensure low off-state leakage current (at the gate voltage of 0 V), even though the fin width of the device is reduced to 30 nm, which would not meet the requirement for low standby power consumption. On the other hand, the FinFET with a 10 nm-thick Al2O3 dielectric layer and a much wider fin width of 100 nm shows normally-off operation with a threshold voltage of 0.8 V, SS of 63 mV/dec, and very low off-state current of 1 nA/mm. When the fin width is reduced to 40 nm, the threshold voltage of the FinFET is increased to 2.3 V and the SS is decreased to 52 mV/decade. These excellent switching performances convince us that the FinFETs might be promising either for low voltage logic or for efficient power switching applications. The observed SS values, which are smaller than the theoretical Boltzmann limit (60 mV/decade), can be explained by the concept of the voltage-dependent effective channel width. [ABSTRACT FROM AUTHOR]

A gallium nitride (GaN)-based normally off metal–oxide–semiconductor field-effect transistor (MOSFET) using a dual-metal-gate (DMG) structure was proposed and fabricated to improve current drivability. Normally off operation with a high Vth of 2.3 V was obtained using a Cl2/BCl3-based recess etching process. The DMG structure was employed to improve current characteristics, which can be degraded by recess etching. The ID and gm of a DMG-based device with nickel (Ni)-aluminum (Al) were improved by 42.1% and 30.9%, respectively, in comparison to the performances of a single-metal-gate-based device with Ni because the DMG structure increased electron velocity in the channel region. This demonstrates that the DMG structure with a large work-function difference significantly improves the carrier transport efficiency. GaN-based recessed-gate MOSFETs based on the DMG structure hold promising potentials for high-efficiency power devices. [ABSTRACT FROM AUTHOR]

The fabrication of a single pixel sensor, which is a fundamental element device for the fabrication of an array-type pixel sensor, requires an integration technique of a photodetector and transistor on a wafer. In conventional GaN-based ultraviolet (UV) imaging devices, a hybrid-type integration process is typically utilized, which involves a backside substrate etching and a wafer-to-wafer bonding process. In this work, we developed a GaN-based UV passive pixel sensor (PPS) by integrating a GaN metal-semiconductor-metal (MSM) UV photodetector and a Schottky-barrier (SB) metal-oxide-semiconductor field-effect transistor (MOSFET) on an epitaxially grown GaN layer on silicon substrate. An MSM-type UV sensor had a low dark current density of 3.3 × 10−7 A/cm2 and a high UV/visible rejection ratio of 103. The GaN SB-MOSFET showed a normally-off operation and exhibited a maximum drain current of 0.5 mA/mm and a maximum transconductance of 30 μS/mm with a threshold voltage of 4.5 V. The UV PPS showed good UV response and a high dark-to-photo contrast ratio of 103 under irradiation of 365-nm UV. This integration technique will provide one possible way for a monolithic integration of the GaN-based optoelectronic devices. [ABSTRACT FROM AUTHOR]

• Normally-off GaN MOSFET is successfully demonstrated by using the selective regrowth of AlGaN layer on source/drain (S/D) regions. • Wide regrown AlGaN layer is applied to GaN MOSFET to accommodate the poor structural quality of narrow regrown AlGaN on the S/D regions. • The proposed device with wide regrown AlGaN S/D has the potential to serve as a robust and uniform normally-off GaN MOSFET. A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and L g of 10 μm shows enhanced electrical performance such as maximum drain current (I D,max) of 57 mA/mm, maximum transconductance (g m,max) of 11 mS/mm, and field-effect mobility (μ FE) of 59 cm2/V·s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO 2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance. [ABSTRACT FROM AUTHOR]

In this paper, we have fabricated and characterized In 0.7 Ga 0.3 As quantum-well (QW) metal-oxide-semiconductor field-effect-transistors (MOSFETs). We have employed the gate dielectric of the Al 2 O 3 /HfO 2 (0.6/2 nm) bi-layer stack by ALD. The fabricated device with L g = 4 μm exhibits a record maximum transconductance ( g m_max ) in excess of 520 μS/μm at >1 μm region, and reasonably good electrostatic integrity, such as SS = 110 mV/decade and DIBL = 43 mV/V. Also, we have investigated the gate length scaling behavior in terms of output, transconductance, and transfer characteristics. In particular, our devices feature very uniform values of the electrostatic integrity, such as SS = 100–110 mV/decade, V T = −0.25 V to −0.2 V and DIBL = 40–50 mV/V, as L g decreases from 10 μm to 4 μm. Furthermore, we have explored the impact of source resistance ( R S ) onto the device characteristics of the InGaAs QW MOSFETs. In doing so, we have modeled both measured extrinsic transconductance ( g m_ext ) and intrinsic transconductance ( g m_int ) as a function of L g . [ABSTRACT FROM AUTHOR]

We present an instability investigation of In 0.7 Ga 0.3 As quantum-well (QW) metal–oxide–semiconductor field-effect-transistors (MOSFETs) on InP substrate with Al 2 O 3 and Al 2 O 3 /HfO 2 gate stacks. The device with bi-layer Al 2 O 3 /HfO 2 gate stack exhibits larger shift in threshold-voltage (Δ V T ) under a constant-voltage-stress condition (CVS), than one with single Al 2 O 3 gate stack. At cryogenic temperature, the device with bi-layer Al 2 O 3 /HfO 2 gate stack also induces worse hysteresis behavior than one with single Al 2 O 3 gate stack. These are mainly attributed to more traps inside the HfO 2 material, yielding a charge build-up inside the HfO 2 gate dielectric. This strongly calls for a follow-up process to minimize those traps within the high- k dielectric layer and eventually to improve the reliability of InGaAs MOSFETs with HfO 2 -based high- k gate dielectric. [ABSTRACT FROM AUTHOR]

AlGaN/GaN fin-shaped field-effect transistors (FinFETs) with variable fin width have been fabricated and characterized. Low-temperature measurements reveal distinct operation modes for wide FinFET, narrow FinFET and planar FET. The wide fin device exhibits broad transconductance ( g m ) that decreases sublinearly with increasing temperature due to the existence of the sidewall metal–oxide–semiconductor (MOS) channel. By comparison, the conventional planar AlGaN/GaN metal–insulator–semiconductor heterostructure FET (MISHFET) features relatively narrow g m curve and near-exponentially decay of g m with temperature. The effect of the sidewall channel becomes more prominent for the narrow fin device and leads to two distinct g m peaks. The first peak at negative gate voltage corresponds to the two-dimensional electron gas (2-DEG) channel, while the second peak at positive gate voltage is related to the sidewall MOS channel. Measurements also show that the electrons in 2-DEG channel experience polar-optical-phonon scattering unlike the electrons in the sidewall MOS channel which are mainly subject to Coulomb scattering. [ABSTRACT FROM AUTHOR]

Abstract: Several types of GaN MOSFETs with normally-off operation have been fabricated on insulating substrate and evaluated. In recessed-gate GaN MOSFET, the threshold voltage (V th) can be easily controlled, but the current drivability is modest and needs to be improved by adopting appropriate device structure and/or process. We achieved enhanced performance by combining the recessed-gate technology with additional processes, such as: (i) the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, (ii) the post-deposition annealing of gate oxide to decrease the gate leakage current, (iii) the re-growth of n+-GaN layer for source/drain to improve the access resistance and V th uniformity, (iv) the stress-control technology to secure high 2-D electron–gas density (2DEG) on source/drain and decrease the series resistance, and (v) the use of the p-GaN back-barrier to decrease the buffer leakage current. We also present the characteristics of GaN-based FinFETs with very narrow fin. [Copyright &y& Elsevier]

Abstract: We proposed models of subthreshold characteristics for deep nanoscale short channel asymmetric junctionless Double-Gate (DG) MOSFETs. Models were derived by solving 2-D Poisson’s equation using variable separation technique. The subthreshold behavior with structure asymmetry such as different gate oxide thicknesses and different gate biases between the front-gate and back-gate can be exactly described. Design parameters such as body doping, body thickness and channel length were considered. The models were verified by comparing with device simulations’ results. [Copyright &y& Elsevier]

Abstract: A unified analytical continuous model, based on an approximate solution of Poisson’s equation, is proposed for the current–voltage (I–V) characteristics of accumulation mode (junctionless FETs) and conventional inversion mode MOSFETs which have symmetric and asymmetric double-gate structures. As a unified model, it is applicable to both junctionless and conventional double-gate (DG) MOSFETs and also represents the I–V characteristics of the MOSFETs with symmetric and asymmetric cases. The model with symmetric and asymmetric gates accounts for body doping, body thickness, and front-gate and back-gate oxide thicknesses. The model is verified by comparing with TCAD simulation results and shows a good agreement. [Copyright &y& Elsevier]

Abstract: We have grown high quality GaN layers on (111)-oriented silicon substrate using a two-step growth method and fabricated high-performance normally-off n-channel GaN Schottky-barrier MOSFET (SB-MOSFET). Indium-tin-oxide (ITO) was used as Schottky-barrier contact for source and drain (S/D) because the work function of ITO is close to the electron affinity of GaN. Due to enhanced crystalline quality and reduced surface roughness of GaN layer grown by two-step process, the fabricated device exhibited much improved performances: sufficiently high threshold voltage of 3.75V, subthreshold slope of 171mV/dec, low specific on-resistance of 9.98mΩcm2, and very high field-effect mobility of 271cm2/Vs. This is the highest mobility value among the GaN MOSFETs ever reported so far. [Copyright &y& Elsevier]

Abstract: We fabricated a normally-off mode n-channel schottky barrier metal oxide semiconductor field effect transistor (SB-MOSFET) with transparent electrodes (ITO, IZO) as source/drain (S/D) contact on a highly resistive GaN layer grown on silicon substrate. Fabricated SB-MOSFET with ITO S/D exhibited as high as 40mA/mm of maximum drain current and a 12mS/mm of maximum transconductance with the threshold voltage of 4.2V, which is far better than that of SB-MOSFET with IZO S/D. The normalized off-current was as low as 10nA/mm. The UV–visible extinction ratio of a MOSFET type UV-sensor was measured over 130 for V DS =5V. ITO was proved as a promising schottky barrier material for GaN MOSFET source and drain not only for the electronic but UV-sensing applications better than IZO for this purpose. [Copyright &y& Elsevier]

Abstract: Normally-off GaN-MOSFETs with Al2O3 gate dielectric have been fabricated and characterized. The Al2O3 layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330mA/mm and the maximum transconductance of 32mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347mV/dec and from 50 to 55cm2 V−1 s−1, respectively. The I D–V G curve shows hysteresis due to oxide trapped charge in the Al2O3 before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750°C. The Al2O3 layer starts to crystallize at a temperature of 850°C and its insulating property deteriorates. [Copyright &y& Elsevier]