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CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed. [ABSTRACT FROM AUTHOR]

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (Δ NIT) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (VG) and drain (VD) biases spanning various modes (VG ≤ and > VD) are simulated for low stress VD (< 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained. [ABSTRACT FROM AUTHOR]

• A fully physical TCAD framework to model the NBTI is validated with differently processes MOSFET measured data. • RD model with ABDWT model for interface trap generation, RDD model for bulk trap generation, ABDWT model for hole trapping is used. • Framework Validation in TCAD in 3D FinFETs and GAA-FETs is in progress. A physics-based framework is incorporated in TCAD to model the primary mechanisms responsible for Negative Bias Temperature Instability (NBTI) in P channel High-K Metal Gate (HKMG) MOSFETs. Three underlying mechanisms are treated including interface trap generation-passivation via a Reaction-Diffusion (RD) model and its charge occupancy via an Activated Barrier Double Well Thermionic (ABDWT) model, hole trapping and de-trapping in pre-existing defects in the gate stack are modeled via an ABDWT model, and bulk trap generation-passivation is modeled via a Reaction-Diffusion-Drift (RDD) model. The framework is used to model measured NBTI time-kinetics for DC stress-recovery and various mixed DC-AC gate pulse segments for planar devices. Furthermore, the same framework is also used to test NBTI behavior in 3D FinFETs. [ABSTRACT FROM AUTHOR]

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nanodevices, there are a number of challenges for characterizing their HCA: the random charge–discharge of traps in gate dielectric causes “within-a-device-fluctuation (WDF),” making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nanodevices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation ( $\sigma )$ and mean value ( $\mu $ ). Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is a little information on the accuracy of the extracted $\sigma $ and $\mu $ . We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of ten traps per device, the extracted $\mu $ and $\sigma $ has an accuracy of ±14% and ±24%, respectively, with a 95% confidence. [ABSTRACT FROM PUBLISHER]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse- \(I\) – \(V\) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias. [ABSTRACT FROM PUBLISHER]

Defects in gate oxide cause breakdown and shorten device lifetime. Early works mainly focused on generation process that converts a precursor into a charged defect. Although it can be neutralized through “recovery,” the defect is still there and will recharge when resuming stress. Recently, we have shown that this is not always the case and some defects can be lost, but a detailed investigation is missing. The central objective of this work is to accurately define and extract the loss, separate it from slowdown, and evaluate their enhancement of device lifetime. Loss is defined as elimination of defects, while slowdown means that recharging a “hardened” precursor takes longer than charging a fresh one. Clear evidences show that losses originate from permanent components, i.e., generated interface states and antineutralization positive charges, while slowdown occurs to both permanent and recoverable components. Loss is thermally accelerated, but slowdown of recoverable component is not. This improved understanding adds slowdown and losses to the existing framework for defects. For the first time, we report that the losses and slowdown enhance device lifetime by a factor of 2.6–4.3, for an allowed threshold voltage shift of 20–45 mV. [ABSTRACT FROM AUTHOR]