TCAD Framework for HCD Kinetics in Low VD Devices Spanning Full VG/VD Space.

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (Δ NIT) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (VG) and drain (VD) biases spanning various modes (VG ≤ and > VD) are simulated for low stress VD (< 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained. [ABSTRACT FROM AUTHOR]