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High-i¾? gate-all-around structure counters the Short Channel Effect SCEs mostly providing excellent off-state performance, whereas high mobility III-V channel ensures better on-state performance, rendering III-V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III-V GAAFET based on self-consistent solution of Schrodinger-Poisson equation is proposed. Using this simulator, capacitance-voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant i¾? and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of InxGa1-xAs, channel doping, and cross-sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel 0.005V/nm for above 10nm fin width and 0.064V/nm for sub-10nm fin width. Simulation suggests that for lower channel doping below 1023m-3, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 1023m-3, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage 0.05V/nm oxide thickness and 0.01V/per unit change in i¾?. Copyright © 2014 John Wiley & Sons, Ltd.

Since the fabrication of first III–V Gate-All-Around (GAA) MOSFET it is under extensive research, as it is one of the potential candidates to replace the state of art tri-gate FinFETs, to continue progressive scaling. In this work, transport characterization of experimentally demonstrated gate-all-around (GAA) In x Ga 1−x As nanowire MOSFET in near-ballistic regime is performed using 3D self-consistent Schrodinger-Poisson solver based on Uncoupled Mode Space approach, taking wave function penetration and other quantum mechanical effects into account. The effects of channel length variation on transport characteristics are also examined.

Gate-all-around structure with III-V channel material shows improved channel performance with high carrier mobility and less short channel effect and therefore is being studied rigorously for next generation transistors. We propose an analytical model to calculate gate capacitance and drain current of gate-all-around (GAA) nanowire MOSFET, a prospective device to replace the state-of-art FinFET in near future as per ITRS roadmap. The gate capacitance in strong inversion region is modeled incorporating quantum mechanical effects which are verified against the results obtained from self-consistent simulation of Schrodinger-Poisson equation appeared in recent literature. This model can also be extended for calculating gate capacitance in strong inversion region of different Multi-gate MOSFETs. A Spice compatible analytic model for drain current is also proposed which shows excellent agreement with the reported results of experimentally demonstrated In 0.53 Ga 0.47 As (2×1016/cm3) GAA MOSFET. Using the proposed formula for gate capacitance in strong inversion region and drain current together with semi-numerical ballistic MOSFET model, the performance of In 0.53 Ga 0.47 As (2×1016/cm3) GAA MOSFET is examined. This device is found suitable for ultra-high performance application with very high intrinsic cut-off frequency resulting from very low gate delay and very high on current and gate capacitance. The proposed analytical model of gate capacitance utilizes a modified form of co-axial cable capacitance along with the quantum capacitance limit to form a computationally efficient formula that is in well agreement with the results appeared in recent literature. On the other hand, Landauer-Buttiker formula and compact model for drain current of planar bulk-MOSFET are utilized to form the model for analytic drain current that shows excellent agreement with the experimental results appeared in the literature in recent past. The proposed model can be used for Spice modeling and circuit simulation of In 0.53 Ga 0.47 As GAA MOSFET. Moreover, this model is flexible and can be modified for other high performance multi-gate nano-devices.

This paper presents the characterization of interface trap charge for 30 nm In0.53Ga0.47As channel Gate-all-around field effect transistor (GAAFET) using ALD Al203 as the oxide. The interface trap charge density (Dit) is extracted from CV model through self consistent iterations. The CV model is formulated by self consistent Schrodinger-Poisson solver. Wave function penetration effect has been considered while solving the Schrodinger equation. The result gives an intuition about the Dit profile. The difference between the initial assumed CV and the final CV demonstrates the effect of Dit on the CV profile of the device. We repeated the same for In.65Ga.35As and In.75Ga.25As and then did a comparative study of the devices. The donor-like traps dominate the Dit profile for higher mole-fraction of In in InGaAs which in our case is In0.75Ga0.25As. The stronger inversion of In-rich channels and hence, better transport characteristics is evident from these results.

The 3-D poisson's equation with eight boundary conditions is solved analytically and an analytical model of potential profile and threshold voltage for rectangular gate-all-around III–V nanowire MOSFET device is developed with quantum correction. Dependence of threshold voltage on channel width, oxide thickness, gate-length, doping and channel material composition are determined from the developed model with experimental and ATLAS verification‥ The model agrees well with experimental and simulation results and offers an insight to the device performance.

This paper presents the ballisitic current limit and gate leakage due to direct tunneling of a Rectangular Gate-all-around InGaAs Nanowire Transistor and their variation with fin width, oxide thickness and In compostion in InGaAs. Ballistic current is found to be higher (1.5×1011 Am−2) for about 20nm fin width, sub-5nm oxide thickness and In-rich InGaAs channel. On the other hand, gate leakage is prominent for sub-4nm oxide thickness, larger fin width and In-rich InGaAs.