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Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance (C Q) which limits the effective gate dielectric reduction. In this work, we analyzed the effect of C Q on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator-metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. C Q contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from C Q, grapheme’s high mobility and low-voltage operation allows for graphene channels suitable for next generation transistors.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

The preparation of uniform large-area highly crystalline organic semiconductor thin films that show outstanding carrier mobilities remains a challenge in the field of organic electronics, including organic field-effect transistors. Quantitative control over the drying speed during dip-coating permits optimization of the organic semiconductor film formation, although the kinetics of crystallization at the air-solution-substrate contact line are still not well understood. Here, we report the facile one-step growth of self-aligning, highly crystalline soluble acene crystal arrays that exhibit excellent field-effect mobilities (up to 1.5 cm V -1 s -1) via an optimized dip-coating process. We discover that optimized acene crystals grew at a particular substrate lifting-rate in the presence of low boiling point solvents, such as dichloromethane (b.p. of 40.0 °C) or chloroform (b.p. of 60.4 °C). Variable-temperature dip-coating experiments using various solvents and lift rates are performed to elucidate the crystallization behavior. This bottom-up study of soluble acene crystal growth during dip-coating provides conditions under which one may obtain uniform organic semiconductor crystal arrays with high crystallinity and mobilities over large substrate areas, regardless of the substrate geometry (wafer substrates or cylinder-shaped substrates). © 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim.

Conductive electrodes and electric circuits that can remain active and electrically stable under large mechanical deformations are highly desirable for applications such as flexible displays, field-effect transistors, energy-related devices, smart clothing and actuators. However, high conductivity and stretchability seem to be mutually exclusive parameters. The most promising solution to this problem has been to use one-dimensional nanostructures such as carbon nanotubes and metal nanowires coated on a stretchable fabric, metal stripes with a wavy geometry, composite elastomers embedding conductive fillers and interpenetrating networks of a liquid metal and rubber. At present, the conductivity values at large strains remain too low to satisfy requirements for practical applications. Moreover, the ability to make arbitrary patterns over large areas is also desirable. Here, we introduce a conductive composite mat of silver nanoparticles and rubber fibres that allows the formation of highly stretchable circuits through a fabrication process that is compatible with any substrate and scalable for large-area applications. A silver nanoparticle precursor is absorbed in electrospun poly (styrene-block-butadiene-block-styrene) (SBS) rubber fibres and then converted into silver nanoparticles directly in the fibre mat. Percolation of the silver nanoparticles inside the fibres leads to a high bulk conductivity, which is preserved at large deformations (σ ≈ 2,200 S cm(-1) at 100% strain for a 150-µm-thick mat). We design electric circuits directly on the electrospun fibre mat by nozzle printing, inkjet printing and spray printing of the precursor solution and fabricate a highly stretchable antenna, a strain sensor and a highly stretchable light-emitting diode as examples of applications.

The strongly correlated thermoelectric properties have been a major hurdle for high-performance thermoelectric energy conversion. One possible approach to avoid such correlation is to suppress phonon transport by scattering at the surface of confined nanowire structures. However, phonon characteristic lengths are broad in crystalline solids, which makes nanowires insufficient to fully suppress heat transport. Here, we employed Si-Ge alloy as well as nanowire structures to maximize the depletion of heat-carrying phonons. This results in a thermal conductivity as low as ∼1.2 W/m-K at 450 K, showing a large thermoelectric figure-of-merit (ZT) of ∼0.46 compared with those of SiGe bulks and even ZT over 2 at 800 K theoretically. All thermoelectric properties were "simultaneously" measured from the same nanowires to facilitate accurate ZT measurements. The surface-boundary scattering is prominent when the nanowire diameter is over ∼100 nm, whereas alloying plays a more important role in suppressing phonon transport for smaller ones.

The composition of amorphous oxide semiconductors, which are well known for their optical transparency, can be tailored to enhance their absorption and induce photoconductivity for irradiation with green, and shorter wavelength light. In principle, amorphous oxide semiconductor-based thin-film photoconductors could hence be applied as photosensors. However, their photoconductivity persists for hours after illumination has been removed, which severely degrades the response time and the frame rate of oxide-based sensor arrays. We have solved the problem of persistent photoconductivity (PPC) by developing a gated amorphous oxide semiconductor photo thin-film transistor (photo-TFT) that can provide direct control over the position of the Fermi level in the active layer. Applying a short-duration (10 ns) voltage pulse to these devices induces electron accumulation and accelerates their recombination with ionized oxygen vacancy sites, which are thought to cause PPC. We have integrated these photo-TFTs in a transparent active-matrix photosensor array that can be operated at high frame rates and that has potential applications in contact-free interactive displays.

Researchers use a pre-orienting layer to achieve nearly single-crystalline GaN pyramidal arrays on amorphous glass substrates. The polycrystalline morphology can be controlled by placing a hole-patterned SiO2 layer on the low-temperature GaN nucleation layer. Light-emitting diodes fabricated by this technique exhibited a luminance of 600 cd m−2.

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.

Scientists describe a size-selective quantum dot patterning technique that involves kinetically controlling the nanotransfer process without a solvent. The resulting printed quantum dot films exhibit excellent morphology and a well-ordered quantum dot structure. This technique allows fabrication of a 4-inch (or larger) thin-film transistor display with high colour purity and extremely high resolution.

For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser crystallization process to grow perfect single-crystal Si layers on the amorphous dielectric Si dioxide layers. The SRAM cell size is 36 F2 and 0.36 ?m2 with 100-nm complementary MOS technology. The 3-D SRAM cell consists of three differently layered and 3-D stacked-cell thin-film transistors (TFTs), whose channel area is a perfect single-crystal Si. The electrical characteristics of the pass n-channel MOS TFT and the load p-channel MOS TFT are very close to those of the planar bulk transistors because their channel Si layers are perfect single-crystal films. A 500-MHz high-performance and highly cost effective 72-Mb-density 3-D SRAM, which is comparable to the conventional planar 6T SRAM in electrical performance, was successfully fabricated for a stand-alone and embedded memory, with this 3-D stacked 6T SRAM cell technology, the low-temperature TFT formation process, periphery-only Co salicidation, and the W shunt wordline scheme.

The purpose of this paper is to attempt to find a plausible solution for a high density FRAM (Ferroelectric Random Access Memory). To complete this, firstly, we give a very brief but an important review of how FRAM technologies have been evolved during the past many years. Secondly, not only are a few examples demonstrated in terms of how a FRAM-embedded system is advantageous when adopted in a system but it is also put forward how FRAM can play an essential role in a fusion memory. Finally, several process technologies for integrating a reliable high-density FRAM are mentioned, accordingly resulting in very reliable cell-charge populations after full integration, along with wafer-level reliabilities.

We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.

A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and improve the th distribution is presented in this paper. The asymmetric S/D structure consists of a diffused junction and inversion layer which is induced by the fringe field of the gate bias voltage during NAND operation. To reduce the area overhead caused by the select transistors, a 64-cell NAND string, which is twice the number of cells used in conventional NAND devices, is also evaluated. The proposed NAND memory device is demonstrated by a 32-Mb test chip which is fabricated using a 60-nm NAND flash technology. It exhibits subthreshold slope characteristics that improved by 37% and a programmed th distribution width that improved by 35% while almost maintaining multiple-level-cell NAND flash performance requirements.

A deep trench isolation (DTI) process with a 4 µm deep trench has been developed and successfully applied to 5-megapixel complementary metal oxide silicon (CMOS) image sensors with a 1.7 µm pixel pitch. It was found that from the results of simulations and experiments, DTI is very effective for reducing electrical crosstalk without degrading other pixel characteristics, such as full well capacity, sensitivity, and white spot density. Therefore, DTI could be a solution for obtaining a high performance for CMOS image sensors with a small pixel size of sub-2.0 µm.

We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.

We developed a 1.6 V FRAM embedded device by successfully implementing a 100 nm MOCVD-PZT capacitor with a SrRuO3 electrode and a novel additional top electrode (ATE). ATE was used for preventing hydrogen-reduction damage or metal substance damage, arising from direct application of Al or W to top electrode. In spite of excellent reliability and wide sensing window of the memory, we found that there was a problem of lift-off of the ATE layer after full integration, leading to bit failure of the product. In order to eliminate the lift-off, we developed a new ATE scheme not only by using a compressive capping- oxide layer but by improving conformal deposition of ATE. The failed bits that appear as a tail of charge distribution were cleared even under a reliability test, a bake for 100 hours at 150°C. As a result, yield loss of the device was greatly reduced.

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

FRAM whose cell structure and operation is almost identical to DRAM, can ideally realize cell size and performance of DRAM. However, the density and performance of current FRAM still fall far behind those of DRAM. In this paper, innovative 1T1C FRAM technologies for ultra high reliable mega density FRAMs and future high density FRAMs are discussed. A novel electrode technology has been proved to guarantee 175°C, 10 years retention lifetime and more than 1E13 endurance lifetime of mega density 1T1C, COB FRAM with the cell size of 15F2 at 250 nm technology node. Furthermore, a cell size of 12F2 at 150 nm technology node has successfully been realized by developing innovative 200 nm thick capacitor stack technologies and novel capacitor etching technologies. Finally, critical issues of 3-D capacitor arising from 3-dimensional deposition, such as step coverage and film uniformity have been greatly improved by the modification of the MOCVD PZT feeding source and a newly introduced noble metal atomic l...

In this study we present an MOCVD-PZT-based 1.6 V operational 1T1C COB FRAM for embedded smart card applications. The extension of FRAM operation to low voltage requires reduction of PZT thickness to 100 nm which is accompanied by a degradation of saturation polarization as well as reliability properties. It will be shown that the application of a seeding layer offers a solution to the reliability problem. The sensing margin of the device is enhanced by a careful optimization of the Ti/(Zr+Ti) ratio of the PZT film.

For ferroelectric random access memory (FRAM) to be beneficial in future mobile devices, high-density FRAM with nm scaled cell should be developed. We have succeeded in scaling further the cell size of one-pass transistor and one-storage capacitor (1T1C) FRAM down to 0.27 µm2 at 150 nm technology node. Owing to new SrRuO3 (SRO) electrode technology along with ultrathin PbZrTiO3 (PZT) using metal organic chemical vapor deposition (MOCVD) technology, two-dimensional (2-D) metal–insulator–metal (MIM) ferroelectric capacitor was successfully scaled down vertically to 200 nm. By the application of a new double hard mask capacitor etching technology, 0.11-µm2-area 200-nm-thick 2-D PZT capacitor was successfully isolated with 180 nm spacing. As a result, a high remanent polarization of 40 µC/cm2 was obtained at 1.6 V on a 0.11 µm2 ferroelectric storage capacitor of the 0.27 µm2 cell 1T1C FRAM. Great advances in three-dimensional (3-D) ferroelectric capacitor, which is essential for 6–8 F2 cell 1T1C FRAM at nm scaled technology node, have been made by introducing a new atomic layer deposition (ALD) method for 3-D electrode and a novel MOCVD PZT deposition for 3-D PZT. As a result, for the first time, robust hysteresis was obtained from a 3-D PZT capacitor.

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.

Highly reliable 32 Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The highly (1 1 1) oriented ferroelectric films were fabricated by the optimized annealing method, which generates large remnant polarization. In addition to the double annealing process for sol–gel derived ferroelectric films, advanced capacitor technology of CVD process was developed for achieving strong retention properties. The CVD technique provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and large sensing margin. After baking test at 150 °C for 100 h, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.

The retention properties were improved by optimizing capacitor process and developing advanced integration process. The retention trends of ferroelectric capacitors before integration were systematically investigated as a function of critical process parameters such as baking temperature and annealing temperature and time. It was found that the ferroelectric capacitors show best retention properties by double annealing process with high baking temperature of 330°C. The optimized ferroelectric capacitors were integrated into 32 Mb FRAM with 0.44 μm2 cell size and 0.25 μm design rule, and evaluated for their retention behavior. Since the retention properties of real cell size capacitors were closely correlated with sensing window, it was focused on enhancing the sensing window by high etching slope and chemical mechanical planarization (CMP) process. It was demonstrated that the retention properties were greatly improved by using optimal capacitor process and advanced integration process.

Current high density FRAM devices have been fabricated by developing several novel integration technologies such as capacitor technology and process technology. The process technology minimizes the integration degradation using stable BC scheme, encapsulating barrier layer (EBL), and effective etching curing process. The capacitor technology generates robust ferroelectric capacitors to be immune to any integration damage by taking advantage of new ferroelectric films and CVD deposition technique. Future FRAM technology will be focused on etchless scheme, nano-scale ferroelectric films, and three-dimensional capacitor scheme using CVD deposition techniques for noble metal electrode with excellent step coverage, which will produces high density 256 Mb FRAM and beyond.

We evaluate different switching behaviors of lead zirconate titanate (PZT) thin film capacitors with two different geometries: one, a square 100×100 μm; the second, a ribbon (1.6 μm width but with approximately the same total area), as a function of temperature T, and applied electric field E. The ribbon capacitor shows a stronger dependence (by ca. 70%) of activation field on T and E. This is interpreted as a chemical reduction of edge material in the long-perimeter ribbons due to plasma etching. In order to understand and model the different domain switching of these two types of PZT capacitor, we also investigate impedance spectra at various temperatures from 27 to 470 °C. From ac conductance spectra, both square- and ribbon-type capacitors have similar trap levels, 0.38±0.02 eV. From analysis of conductivity spectra, we find that the ribbon capacitor contains an additional 0.19±0.02 eV trap level attributed to H–O dipoles due to hydrogen reduction; the latter trap results in domain pinning, which is i...

We report on the measurements of reliability of 0.25 μ m 15F2 cell FRAM using novel MOCVD PZT technology. The MOCVD PZT capacitors were prepared using a pre-purging process and successfully integrated into the 32 Mb FRAM process with double EBL technology and optimal ILD/IMD scheme. After full integration, the 0.44 μ m2 MOCVD PZT capacitors with a 2Pr value of 35 μ C/cm2 at an applied voltage of 2.7 V show superior retention properties. The MOCVD PZT cells have large sensing windows of 420 mV at an operation voltage of 2.7 V. The sensing windows show only a slight decrease during 100 hours of baking at a temperature of 150°C, after which not a single cells is observed to fail. Therefore, it is clearly demonstrated that using the novel MOCVD PZT capacitors, high reliability of 0.25 μ m 15 F2 cell FRAM can be achieved.

We discuss the correlation between intermetallic dielectric (IMD) processes and electrical properties of fully integrated ferroelectric cells. The best IMD scheme for higher density FRAM devices is proposed regarding gap-filling properties of narrow metal pitches and electrical characteristics. The used oxides were i)HDP, ii)HDP/POX, and iii)PSG/SOG/USG. HDP possesses good gap-filling characteristics due to the simultaneous application of deposition and etching. However it generates large plasma loads to the wafer, resulting in an undesired degradation of the 2Pr values. The HDP/POX stacks employ an additional POX oxide buffer layer in order to minimize damage due to the HDP deposition process, but the application of the double stack structure shows the same degradation as the HDP-only scheme. However, PSG/SOG/USG stack showed good gap-filling characteristics as well as lower 2Pr degradation. In the triple stack, PSG and USG act as a main IMD layer and as an oxide buffer for SOG coating, respectively. In ...

New type of nonvolatile memories like FRAM, PRAM, MRAM which are capable of fast and unlimited write can ideally perform next generation high level mobile functions and are being focused as candidates for next generation mobile memory. Among new memory candidates, MRAM has the fastest speed, FRAM has the lowest power consumption and PRAM has excellent cell scalability. Such unique feature of each new memory candidate will be effectively utilized in next generation mobile electronics where memory function will be very diversified and specified as well as unified. In this paper, new memory technologies will be viewed in respect of current technology status, technical challenges encountered, and the solution for technology barriers.

Since current 32 Mb high-density ferroelectric random access memory (FRAM) shows very narrow sensing window, it is strongly desired to improve the sensing widow for generating a reliable high yield. In this paper, we propose a TiAlN oxygen stopping layer for enhancing the diffusion barrier layer, which makes it possible to reduce the bottom stack height from 180 nm to 90 nm, resulting in the increase of effective cell area and cell charge. In addition to the enhanced diffusion barrier, we developed a stable PE-SiN etch stopper for replacing Ir noble metal etch stopper that has strong stress variation and eventually deteriorates the cell charge distribution. By using TiAlN oxygen stopping layer and PE-SiN etch stopper, the 32 Mb FRAM device shows very wide sensing window of 100 fC, which guarantees a reliable high yield.

In order to manufacture high-density ferroelectric random access memory (FRAM) device, it is required to develop one mask capacitor etching technology, because it can provide greatly reduced cell size. However, as the capacitor size shrinks further, the influence of etching damage on the ferroelectric properties becomes much serious due to the high ratio of perimeter/area for patterned capacitor. Since undesired polymeric etch byproducts were formed on sidewall of the edge cell capacitors in 32 Mb FRAM with 0.25 μm design rule, we developed novel post-etch curing technology using O2 plasma treatment with wet cleaning process. After the post-etch curing treatment, the hysteresis loops of block edge cells were almost identical to those of block center cells, which results in improving the relative 2Pr value as ratio of edge cells/center cells from 33% to 98%. In conclusion, novel curing technology was successfully developed for one mask etching damaged ferroelectric capacitor using O2 plasma treatment with ...

In the 0.25 μm FRAM technology generation, it is extremely difficult to define the hole-type cell via on very small top electrode area, because there is no process margin for the hole type cell via. Therefore, a runner via technology based on line-type cell via with Ir etch stopper is developed for 0.25 μm FRAM technology generation. However, it was found that the severe charge degradation occurred during the runner cell via process. It was found that the stress of Ir film plays a dominant role in degrading the capacitor value. Since the Ir film shows severe severe stress variation from compressive to tensile during heating and cooling, the ferroelectric capacitors using the Ir etch stopper show the charge degradation during integration. Therefore, we developed a common cell via scheme and stable PE-SiN etch stopper which possess compressive stress and high etching selectivity against PSG film for replacing Ir etch stopper. The polarization value of ferrolectric capacitor was not degraded after etch-stopp...

High performance cell transistor was proposed for long data retention time in mass-produced 512 Mb dynamic random access memory (DRAM) with 0.12 µm design rule. Since process-induced trap density and electric field at the storage node junction should be reduced to improve data retention time, we designed a cell transistor using localized channel and field implantation (LOCFI) scheme. Using LOCFI scheme, the data retention time was nearly doubled by virtue of reduced cell leakage current resulting from the suppressed ion implantation damage and the reduced electric field at the storage node simultaneously. In addition, it was found that the hydrogen annealing after trench etching, the double gate spacer consisting of CVD oxide and Si3N4 layer, and the chemical downstream Si treatment after storage node contact etching significantly improved the data retention time. These proposed approaches for longer data retention time can be applied to future high density DRAMs with feature size down to 0.1 µm range.

Since the space margin between capacitors has been greatly reduced in 32 Mb high-density ferroelectric random access memory (FRAM) with a 0.25 µm design rule, considering the limitation of current etching technology, the stack height of ferroelectric capacitors should be minimized for stable node separation. In this paper, novel capacitors with a total thickness of 4000 A were prepared using a seeding layer, low temperature processing, and optimal top electrode annealing. The 1000 A Pb(Zr1-xTix)O3 (PZT) films showed excellent structural and ferroelectric properties such as strong (111) orientation and large remanent polarization of 40 µC/cm2. The low stack capacitors were then implemented into 0.6 µm and prototype 0.25 µm FRAM. Compared to a conventional capacitor stack, the ferroelectric capacitors exhibited adequate sensing margin of 250 fC, thus giving rise to a fully working die of 4 Mb FRAM. Therefore, it was clearly demonstrated that the novel capacitors can enable the realization of a high-density 32 Mb FRAM device with a 0.25 µm design rule.

Current and future FRAM technologies are reviewed and discussed for developing high density FRAM devices as stand-alone memory application. In order to enter into mainstream of memory devices, FRAM devices should achieve such small cell size factor of ∼8F 2 , strong reliability, and design optimization. The low cell size factor can be realized by using etchless capacitor technology, ultra thin capacitor technology, and runner via technology. The reliability can be acquired by Pt-inserting technology. Finally, high density FRAM device can be accomplished by design optimization.

Ferroelectric capacitors are severely degraded by integrating interlayer dielectrics (ILD) and intermetallic dielectrics (IMD) due to their undesired hydrogen attack and stress effect. In this paper, it was found that the dielectrics film stress plays more dominant role in degrading submicron 32Mb ferroelectric capacitors (0.48 2 0.92 w m 2 ) than hydrogen attack due to the Ir ATE electrode, which works for blocking hydrogen attack, but generates sever stress variation. Since the Ir film shows severe stress variation from compressive to tensile during heating and cooling cycles, it is desired to prepare compressive ILD and IMD films for compensating the tensile stress. Using P-OX films with compressive stress, the 32Mb ferroelectric capacitors show excellent hysteresis loops with the P r value of 15 w C/cm 2 after completing full integration, which is comparable to 18 w C/cm 2 before the integration. The submicron ferroelectric capacitor prepared by compressive P-OX ILD and IMD materials was successfully ...

As the capacitor size greatly decreases from 1.44 in 4Mb to 0.44 w m 2 in 32Mb FRAM, the hydrogen-damage is severely increased, thus giving rise to the difficulty in protecting the ferroelectric capacitor from the hydrogen attack by using conventional encapsulating barrier layers (EBL). Therefore, it is strongly required to reduce the hydrogen-induced degradation of very small ferroelectric capacitor during the backend integration process. In this paper, we developed double EBL technology by covering whole ferroelectric capacitors again after the Cap-EBL process. The Al 2 O 3 ILD-EBL layer was prepared again after depositing inter-layer dielectrics (ILD) layer, thus eliminating further hydrogen damage during inter-metal dielectrics (IMD) process. Using the double EBL technology, the fully integrated ferroelectric capacitor for 32Mb FRAM exhibits excellent ferroelectric properties such as remnent polarization of 15 w C/cm 2 at 3V. As a result, novel hydrogen-damage free 0.25 w m 15F 2 32Mb FRAM was success...

In this paper, we propose a novel cell transistor using retracted Si/sub 3/N/sub 4/-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-/spl mu/m technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si/sub 3/N/sub 4/-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-/spl mu/m technology and beyond.

A ultraviolet (UV) process is commonly used in fabricating memory devices such as DRAM and SRAM without degrading the memory properties. However, in high density FRAM, the effect of UV light on ferroelectric properties has never been confirmed in real functional FRAM devices FRAM. Therefore, in this paper, we investigated the UV effect on ferroelectric properties and established an optimal back-end process for 1T1C 4Mb FRAM. It was found that the UV light illumination has strong influence on the hysteresis loop of ferroelectric capacitors. The polarization of the capacitor decreased and coercive voltage shifted after exposure to the UV light. It might be attributed to the fact that UV light generates free space charges in the ferroelectric layer and these charges are trapped at the electrode/ ferroelctric interface of the ferroelectric capacitor.

It is well known that ferroelectric capacitors are degraded during etching process due to its highly energetic ion bombardment. The etching damage is considered as the major cause of degrading the ferroelectric properties. In order to achieve high yield of 4Mb FRAM, the etching damage should be minimized. Therefore, it is strongly desired to develop a new etching mask technology for reducing the severe etching damage. In this paper, we investigated several etching mask technologies to choose proper mask for etching the noble metal layers. It was found that TiO2/PSG/TiN and PSG/TiN masks are very effective in minimizing the etching damage and enhancing the etching ability. The Pr value of etch-damaged cell was greatly improved from 5 μC/cm2 to 25 μC/cm2 by using the novel etching masks, resulting in high yield of 4Mb FRAM. As observed in TEM pictures, the ferroelectric capacitors prepared by TiO2/PSG/TiN and PSG/TiN masks are completely protected by the new mask technology.

Ferroelectric random access memory (FRAM) has been pursed as a new standalone memory due to its ideal memory properties such as fast random access in read/write mode and non-volatility with unlimited usage. However, FRAM has only achieved a limited success in limited applications because current FRAM is far behind its inherently outstanding properties. Recently, mega-bit density scaled FRAMs have been developed for creating big market. Many essential technologies have been built with the mega-bit density devices. Among those technologies, 1T1C COB (capacitor over bit line) cell structure is the most important because it can greatly reduce the cell size of FRAM compared to previous and current 2T2C FRAM. Although the recent demonstration gives a promising future for stand-alone FRAM application, current 1T1C COB FRAM still has incomparably large cell size factor compared to DRAM and Flash. This is one of the most challenging issues that FRAM faces for developing high-density stand-alone memory. Be...

The retention property of PZT (PbTixZr1-xO3) films has been a major obstacle to commercial FRAM (Ferroelectric Random Access Memory) prodeucts. The retention phenomenon is mainly due to undesired interfacial layers or defects such as oxygen vacancy or Pb vacancy, which is generated by fabricating PZT films. In sol-gel process, the undesired layer is formed at the surface of the PZT films during the annealing process, which greatly degrades the retention property. It was found that the degradation of retention property is caused by a Pb-deficient and Zr-rich layer with high defect density on the surface of PZT film. The undesired surface layer was clearly removed by adopting a novel surface-cleaning technique. The surface-modified PZT films showed excellent Qos value of 34 μC/cm2 after baking for 175 hours at 125°C, which is about 4 times larger than that of as-grown PZT film. The Qos-rate of the surface-modified PZT film was about-9%, which is about one third of that of as-grown PZT film. In spit...

The COB (capacitor-over-bit line) structure is essential for integrating high density FRAM (ferroelectric random access memory) device. It is very difficult in the COB cell structure to maintain low contact resistance between plug material and bottom electrode during the integration processes. We have used CoSix/poly-Si and Pt/IrO2/Ir as plug materials and bottom electrode stack, respectively. However, random single-bit failure was observed due to the high contact resistance, which was caused by the formation of amorphous oxide layer, especially, during high temperature anneal for PZT (Pb[Tix,Zr1-x]O3) crystallization. It was observed that silicon atoms diffuse even into Ir oxygen barrier, thus leading to the oxide formation between the plug and Ir oxygen barrier. The approach we have taken to prevent contact resistance failure is to optimize the plug material that has high endurance against oxidation reaction. In this study, we developed tungsten plug technology to eliminate the random single-bi...