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The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage (Vth) distribution of the IGZO thin film transistors. The total BTS ΔVth and the Vth distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict Vth instability of IGZO TFTs.

A power efficient 20 GHz PLL for 60 GHz transceiver is presented in this paper. The proposed PLL consists of low phase noise voltage controlled oscillator, low power consumption divider chain, phase frequency detector, charge pump, and loop filter. The PLL covers frequency from 19.43 GHz to 20.62 GHz with 2-bit switched capacitor banks. Implemented in 65 nm CMOS technology, the fully integrated PLL occupies an area of 1.3mm2. A phase noise of PLL is −102.05 dBc/Hz at 1 MHz offset frequency and a figure of merit of −174.35 dBc/Hz with 23.6 mW power consumnption.

High-performance, air-stable, p-channel WSe2 top-gate field-effect transistors (FETs) using a bilayer gate dielectric composed of high- and low-k dielectrics are reported. Using only a high-k Al2O3 as the top-gate dielectric generally degrades the electrical properties of p-channel WSe2, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high-k oxide forming is deposited. As a result, a top-gate-patterned 2D WSe2 FET is realized. The top-gate p-channel WSe2 FET demonstrates a high hole mobility of 100 cm2­ V−1 s−1 and a ION/IOFF ratio > 107 at low gate voltages (VGS ca. −4 V) and a drain voltage (VDS) of −1 V on a glass substrate. Furthermore, the top-gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high-k oxide/low-k organic bilayer dielectric is advantageous over single-layer high-k dielectrics for top-gate p-channel WSe2 FETs, which will lead the way toward future electronic nanodevices and their integration.

We have fabricated dual gate field effect transistors (FETs) with 12 nm-thin black phosphorus (BP) channel on glass substrate, where our BP FETs have a patterned-gate architecture with 30 nm-thick Al2O3 dielectrics on top and bottom of a BP channel. Top gate dielectric has simultaneously been used as device encapsulation layer, controlling the threshold voltage of FETs as well when FETs mainly operate under bottom gate bias. Bottom, top, and dual gate-controlling mobilities were estimated to be 277, 92, and 213 cm(2)/V s, respectively. Maximum ON-current was measured to be ∼5 μA at a drain voltage of -0.1 V but to be as high as ∼50 μA at -1 V, while ON/OFF current ratio appeared to be 3.6 × 10(3) V. As a result, our dual gate BP FETs demonstrate organic light emitting diode (OLED) switching for green and blue OLEDs, also demonstrating NOR logic functions by separately using top- and bottom-input.

Molybdenum disulfide (MoS2) nanosheet, one of two-dimensional (2D) semiconductors, has recently been regarded as a promising material to break through the limit of present semiconductors. With an apparent energy band gap, it certainly provides a high carrier mobility, superior subthreshold swing, and ON/OFF ratio in field-effect transistors (FETs). However, its potential in carrier mobility has still been depreciated since the field-effect mobilities have only been measured from metal–insulator–semiconductor (MIS) FETs, where the transport behavior of conducting carriers located at the insulator/MoS2 interface is unavoidably interfered by the interface traps and gate voltage. Moreover, thin MoS2 MISFETs have always shown large hysteresis with unpredictable negative threshold voltages. Here, we for the first time report MoS2-based metal semiconductor field-effect transistors (MESFETs) using NiOx Schottky electrode which makes van der Waals interface with MoS2. We thus expect that the maximum mobilities or ...

Photodiodes made from core–shell nanowires (NWs) comprising n-type silicon (n-Si; core) and nitrogen-doped ZnO (ZnO:N; shell) were fabricated by atomic layer deposition of ZnO:N on vertically aligned Si NWs. The device properties were investigated as functions of nitrogen content of the ZnO:N shell. The electron-carrier concentration of ZnO:N was modulated by adjusting the concentration of the reactant, diluted ammonium hydroxide, from 0 to 30%. The rectification ratio and the reverse-current density of the ZnO:N/n-Si planar heterojunction were evaluated under dark condition for various NH4OH concentrations. The ZnO:N/n-Si heterojunction prepared with NH4OH 15% was found to have the lowest reverse-current density with a moderate resistivity. In order to realize an effective ZnO:N/n-Si photodiode, a ZnO:N layer prepared with 15% NH4OH was deposited on well-aligned Si nanowires. The core–shell NW photodiode showed more sensitive photodetecting performance in UV light than the planar photodiode. Also, the significantly enhanced performances of the core–shell NW photodiode were evaluated by examining its spectral responsivity.

This paper presents a 60-GHz low-profile, wide-band, and high-gain E-shaped patch array with parasitic patches for 60-GHz band. To enhance the bandwidth with low-profile single layer structure, E-shaped patch antenna is applied to form a two resonance frequencies. To increase the antenna gain, parasitic patches are adopted to E-shaped patch array for additional radiation of the antenna array. The height of the antenna is 250um, and the realized gain, 3-dB bandwidth, and impedance bandwidth is 20.2dBi, 20.2%, and 23.7%, respectively.

This paper presents a 120 GHz low-power down converter in a 65 nm complementary metal-oxide-semiconductor (CMOS) process for chip to chip communication. The center frequency of the down converter is 120 GHz. The proposed down converter consists of an active balun, a down conversion mixer, and a baseband amplifier. The average insertion loss of the active balun was − 1 dB within a 3 dB bandwidth. The down conversion mixer achieved a conversion gain of − 13 dB with a local oscillator (LO) power of as small as − 10 dBm. The peak gain of the baseband amplifier was 28.3 dB with a 3 dB bandwidth of 7.7 GHz. This down converter achieves a high conversion gain of 14.3 dB with an LO power of − 10.6 dBm. The proposed down converter consumes 25 mW and has a chip size of 0.89 mm2.

Although organic field-effect transistors (OFETs) have various advantages of lightweight, low-cost, mechanical flexibility, and nowadays even higher mobility than amorphous Si-based FET, stability issue under bias and ambient condition critically hinder its practical application. One of the most detrimental effects on organic layer comes from penetrated atmospheric species such as oxygen and water. To solve such degradation problems, several molecular engineering tactics are introduced: forming a kinetic barrier, lowering the level of molecule orbitals, and increasing the band gap. However, direct passivation of organic channels, the most promising strategy, has not been reported as often as other methods. Here, we resolved the ambient stability issues of p-type (heptazole)/or n-type (PTCDI-C13) OFETs and their bias-stability issues at once, using DNA-base small molecule guanine (C5H5N5O)/Al2O3 bilayer. The guanine protects the organic channels as buffer/and H getter layer between the channels and capping Al2O3, whereas the oxide capping resists ambient molecules. As a result, both p-type and n-type OFETs are simultaneously protected from gate-bias stress and 30 days-long ambient aging, finally demonstrating a highly stable, high-gain complementary-type logic inverter.

Two-dimensional heterojunction diodes with WSe2 and MoS2 nanoflakes respectively as p- and n-type semiconductors were fabricated on both glass and SiO2/p+-Si by direct imprinting. Superior electrostatic and dynamic performances were acquired from the diode on glass when an electric dipole-containing fluoropolymer was employed for encapsulation: forward and reverse current toward ideal behavior, enhanced aging/ambient stability, and improved dynamic rectification resulted.

When the width of a graphene nanoribbon (GNR) is only a few nanometers, it possesses semiconducting properties that enable various high-end electronic applications. In this study, we report that the dense and stable dispersion of a natural graphite formed using flavin mononucleotide (FMN) as a surfactant produces GNRs as small as 10 nm in width. High-resolution transmission electron microscopy reveals GNRs with various widths, along with a graphene flake containing straight-edged GNRs and cuts, depending on substrate treatments. Such nanoribbon formation originates from sonochemical graphene unzipping with a one-dimensional FMN supramolecular ribbon as a template. Raman spectroscopy demonstrates the universal intensity ratio of D over D′ bands near 4, supporting formation of continuous edge defect. Thermal annealing enhances the optical contrast and van der Waals interactions of the graphene film, resulting in increased conductivity compared to the as-prepared graphene film, which is also better than that of reduced graphene oxide.

Two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistors (FETs) have been extensively studied, but most of the FETs with gate insulators have displayed negative threshold voltage values, which indicates the presence of interfacial traps both shallow and deep in energy level. Despite such interface trap issues, reports on trap densities in MoS2 are quite limited. Here, we probed top-gate MoS2 FETs with two- (2L), three- (3L), and four-layer (4L) MoS2/dielectric interfaces to quantify deep-level interface trap densities by photo-excited charge collection spectroscopy (PECCS), and reported the result that deep-level trap densities over 1012 cm−2 may exist in the interface and bulk MoS2 near the interface. Transfer curve hysteresis and PECCS measurements show that shallow traps and deep traps are not that different in density order from each other. We conclude that our PECCS analysis distinguishably provides valuable information on deep level interface/bulk trap densities in 2D-based FETs.

The adhesion of porcelain to zirconia is a key factor in the success of bilayered restorations. In this study, the efficacy of a novel experimental liner (EL) containing zirconia for improved bonding between zirconia and veneering porcelain was tested. Four ELs containing various concentrations (0, 3.0, 6.0, and 9.0 wt %) of zirconia were prepared. Testing determined the most effective EL (EL3 containing 3.0 wt % zirconia) in terms of shear bond strength value (n = 15). Three different bar-shaped zirconia/porcelain bilayer specimens were prepared for a three-point flexural strength (TPFS) test (n = 15): no-liner (NL), commercial liner (CL), and EL3. Specimens were tested for TPFS with the porcelain under tension and the maximum load was measured at the first sign of fracture. The strength data were analyzed using one-way ANOVA and Tukey’s test (α = 0.05) as well as Weibull distribution. When compared to NL, the CL application had no effect, while the EL3 application had a significant positive effect (p < 0.001) on the flexural strength. Weibull analysis also revealed the highest shape and scale parameters for group EL3. Within the limitations of this study, the novel ceramic liner containing 3.0 wt % zirconia (EL3) significantly enhanced the zirconia/porcelain interfacial bonding.

Assembly using a bolt and nut, and rivet or pin have been used widely for forming mechanical joints. The indent method is an easier process than other manufacturing techniques and the toughness of the material is excellent. On the other hand, there are many cases in which the cracks occur on the manufacturing process as the indent method. Therefore, two kinds of models, in which a pin goes into and out PCB plate in this study were developed using the CATIA program and finite element methods were performed using the ANSYS program. When a pin was passed through a PCB plate in cases 1 and 2, the maximum loads applied to the PCB plate were 79.708N and 90.277N, respectively. When the PCB plate came out of the pin in cases 1 and 2, the maximum loads were 63.783N and 33.75N, respectively. The damage prevention and durability can be improved by applying the study results to the design of real indentation.

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed.

A highly efficient n-ZnO/p-Si core–shell nanowire (NW) photodiode was fabricated using ZnO grown by atomic layer deposition (ALD) on a well-ordered Si NW array. Si NW arrays were prepared by metal-assisted chemical etching, for which a metal mesh with a well-organized nanohole array was made using anodic aluminum oxide. This resulted in a good arrangement, smooth surface, and small diameter distribution of the Si NW array. Consequently, ZnO layers with various thicknesses from 15 to 30 nm were deposited by the ALD method. Because of the smooth surface of the well-ordered Si NWs yielding low surface roughness scattering, the resulting photodiode showed significantly improved device characteristics.

Lightweight parts with very uniform precision are manufactured by an indent method and the press technique has been improved. Upon assembly with an indent method, a deformation force due to the compressive force occurs between the pin and hole and the contact surface is affected by damage. Therefore, a 3 dimensional model was made using the CATIA program and the damage on the surface contacted with indent was estimated through the ANSYS program in this study. In the analysis result, the maximum load applied at the PCB plate was 21.3 N when the pin goes through the PCB plate. When PCB plate came out of the pin, the maximum load was 19.24 N. As the structural analysis result, the maximum equivalent stress of Pin 1 was 192.96MPa because the maximum stress occurs at Pin 1 among all parts of this study model. By examining the damage property of the contacted indent and applying this study result to the design of real indentation, the damage can be prevented and the durability can be estimated.

Cellulosic substances in polymer matrices are immiscible and non-dispersive because of mismatch between their surface properties. In order to fabricate a natural fiber-reinforced plastic, hydrophilic cellulosic substances should be modified to hydrophobicity to make it miscible and dispersible to polymer matrices. Herein, this work shows potential application of vapor-phase-assisted surface treatment as a new modification approach for cellulosic substances. Cellulosic substances were modified to improve the compatibility in the polymer matrix. The modified cellulose substrates were characterized by Fourier transform infrared spectrometer spectroscopy, thermogravimetric analysis, and scanning electron microscope, and the resulting shows the grafting polymer on cellulosic substances indeed. To more enhance compatibility in polymer matrix, grafting of the methacryloyl groups on cellulose substance was prepared through gaseous methacrylic anhydride on cellulose surface, and then higher modified cellulose subs...

We investigated the device properties of ZnO homojunction core–shell nanorods (NRs) ultraviolet (UV) photo-detecting diodes depending on fabrication process. ZnO homojunction core–shell NRs fabrication was realized by atomic layer deposition (ALD) of highly conformal ZnO shell with high concentration of nitrogen (HNZO) over hydrothermally synthesized n-ZnO NRs. ALD of HNZO was carried out using diethyl zinc (DEZ) and diluted ammonium hydroxide (NH 4 OH) as a Zn precursor and reactant/nitrogen source, respectively. On the electrical analysis, HNZO films is found to be weak n-type or ambiguous and, finally this HNZO attributed the rectifying property at the junction with n-type ZnO NRs. ZnO planar device was also fabricated as a comparative reference. Comparative study between core–shell and planar device has shown that the responsivity of the core–shell device was turned out to be about two times higher than that of planar device. Photoluminescence (PL) intensity of core–shell device was significantly reduced compared to that of planar device for overall region of wavelength, which was attributed to rapid separation of photo-generated carriers. The carrier transport mechanism in core–shell NR device is discussed based on band bending phenomenon.

DNA-base small molecules of guanine, cytosine, adenine, and thymine construct the DNA double helix structure with hydrogen bonding, and they possess such a variety of intrinsic benefits as natural plentitude, biodegradability, biofunctionality, low cost, and low toxicity. On the basis of these advantages, here, we report on unprecedented useful applications of guanine layer as hydrogen getter and charge trapping layer when it is embedded into a dielectric oxide of n-channel inorganic InGaZnO and p-channel organic heptazole field effect transistors (FETs). The embedded guanine layer much improved the gate stability of inorganic FETs gettering many hydrogen atoms in the gate dielectric layer of FET, and it also played as charge trapping layer to which the voltage pulse-driven charges might be injected from channel, resulting in a threshold voltage (Vth) shift of FETs. Such shift state is very ambient-stable and almost irrevocable even under a high electric-field at room temperature. So, Boolean logics are nicely demonstrated by using our FETs with the guanine-embedded dielectric. The original Vth is recovered only under high energy blue photons by opposite voltage pulse (charge-ejection), which indicates that our device is also applicable to nonvolatile photo memory.

DNA polymers have been studied in the research areas of information and nanotechnology as well as biotechnology with various benefits such as natural plenitude, biodegradability and low toxicity. Here we demonstrate a charge injection type non-volatile memory field-effect transistor (FET) with one DNA-base small molecule, guanine, which is coupled with a MoS2 nanosheet channel as a trapping or charge injection layer material. Owing to the unique properties of the guanine layer and the extremely thin MoS2 nanosheet, our non-volatile memory MoS2 FETs exhibit a more than 3 V memory window under a 35 V/−15 V gate voltage pulse for Program/Erase (or trapping/detrapping), maintaining a high Program/Erase ratio of ∼103 for longer than 1000 s at least. Superior dynamic Program/Erase cycles were performed with a memory inverter composed of two memory FETs connected in series. Such non-volatile memory properties have been mostly well observed even after 45 days, since the trapped electron charges were stably stored in the guanine layer.

Small molecule pentacene layer has been a representative among many organic thin-film transistor (OTFT) channels with decent p-type mobilities, but it is certainly light-sensitive due to its relatively small highest occupied molecular orbital-lowest unoccupied molecular orbital (HOMO-LUMO) gap (1.85 eV). Although a few other small molecule-based layers have been reported later, their photo-stabilities or related device applications have hardly been addressed. Here, a new photostable organic layer is reported, heptazole (C26H16N2), which has almost the same HOMO level as that of pentacene but with a higher HOMO-LUMO gap (≈2.95 eV). This heptazole OTFT displays a decent mobility comparable to that of conventional amorphous Si TFTs, showing good photostability unlike pentacene OTFTs. An image pixel driving the photostable heptazole OTFT connected to a pentacene/Al Schottky photodiode is demonstrated. This heptazole OTFT also conveniently forms a logic inverter coupled with a pentacene OTFT, sharing Au for source/drain.

The stabilities of a blending type organic thin-film transistor with phase-separated TIPS-pentacene channel layer were characterized under the conditions of negative-bias-stress (NBS) and positive-bias-stress (PBS). During NBS, threshold voltage (Vth) shifts noticeably. NBS-imposed devices revealed interfacial trap density-of-states (DOS) at 1.56 and 1.66 eV, whereas initial device showed the DOS at only 1.56 eV, as measured by photoexcited charge-collection spectroscopy (PECCS) method. Possible origin of this newly created defect is related to ester group in PMMA, which induces some hole traps at the TIPS-pentacene/i-PMMA interface. PBS-imposed device showed little Vth shift but visible off-current increase as "back-channel" effect, which is attributed to the water molecules trapped on the TFT surface.

We report on the fabrication of top-gate phototransistors based on a few-layered MoS2 nanosheet with a transparent gate electrode. Our devices with triple MoS2 layers exhibited excellent photodetection capabilities for red light, while those with single- and double-layers turned out to be quite useful for green light detection. The varied functionalities are attributed to energy gap modulation by the number of MoS2 layers. The photoelectric probing on working transistors with the nanosheets demonstrates that single-layer MoS2 has a significant energy bandgap of 1.8 eV, while those of double- and triple-layer MoS2 reduce to 1.65 and 1.35 eV, respectively.

We demonstrated a vertically stacked complementary thin-film transistor inverter (VS-CTFT inverter) for the purpose of maximizing potentials beyond logic applications by including photo-gating and ferroelectric memory operation with properly selected organic and oxide materials. For our VS-CTFT inverter for logic and photo-gating, we used a thermally-evaporated p-channel pentacene layer, sputter-deposited n-channel GaZnSn-based oxide (GZTO), and atomic layer deposited (ALD) Al 2 O 3 dielectric. As a more advanced hybrid approach, we also adopted a ferroelectric poly(vinylidene fluoride/trifluoroethylene) [P(VDF–TrFE)] layer for a CTFT nonvolatile memory inverter with a pentacene memory TFT which is vertically stacked on a top-gate GZTO TFT. Our VS-CTFT inverter nicely displays effective photo- and electrical-gating with a high voltage gain, dynamically operating in the low-voltage regime of 3, 5, and 8 V. The ferroelectric memory inverter as an ultimate hybrid device form demonstrates promising retention properties as triggered by ±20 V gate pulses.

Ga–Sn–Zn–O (GTZO) thin films were prepared on glass substrates at 100 °C by co-sputtering of Ga-doped ZnO and SnO2 targets. Characteristic properties of the films were investigated with varying oxygen gas content in the sputtering ambient. Whereas amorphous GTZO films were prepared with pure Ar sputtering, polycrystalline films were obtained with the addition of oxygen gas. With a proper mixing ratio of sputtering gases, O2/(Ar + O2) ∼2%, we could obtain GTZO films with good performances as an active channel material in thin film transistor (TFT); i.e, field effect mobility of 12.2 cm2 V−1 s−1, on/off current ratio of 109, and subthreshold voltage swing of 0.46 V decade−1.

Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications.

Surface potential measurement on atomically thin MoS2 flakes revealed the thickness dependence in Schottky barriers formed between high work function metal electrodes and MoS2 thin flakes. Schottky diode devices using mono- and multi- layer MoS2 channels were demonstrated by employing Ti and Pt contacts to form ohmic and Schottky junctions respectively. Characterization results indicated n-type behavior of the MoS2 thin flakes and the devices showed clear rectifying performance. We also observed the layer dependence in device characteristics and asymmetrically enhanced responses to NH3 and NO2 gases based on the metal work function and the Schottky barrier height change.

We report on a characterization method to quantitatively estimate the interfacial trap density of states (DOS) in thin-film transistors (TFTs): photon-probe capacitance-voltage (CV) measurement. The photo-CV method was compared to photoexcited charge-collection spectroscopy, which is another photon-probe method using current-voltage (I-V) measurement to meet the same purpose. Here, we directly characterized the DOS of amorphous-Si- and amorphous-InGaZnO-based TFTs using the photon-probe CV measurement, and the results turned out to mainly focus the trap DOS at channel/dielectric interface. On the one hand, the DOS profile by photon-probe I-V method appeared to give additional trap information from the transistor back channel.

We report that a pulsed negative bias stress slightly deteriorates the photoelectric stability of amorphous InGaZnO thin-film transistors, whereas a dc negative bias stress induces a large threshold voltage shift under the light. In the case of pulsed bias stresses, many of photoexcited positive charges might be recombined during the interval between pulses while those charges under dc bias drift to the channel interface without recombination. Interfacial trap density measurements explain the effects of such photoexcited positive charges on the interface.

We report on the fabrication of Ga–Sn–Zn–O thin-film transistors (GTZO-TFTs) and their inverter application. For the most stable and highly-performing GTZO-TFT, an optimal oxygen pressure condition was extracted out during co-sputter deposition of Ga-doped ZnO and SnO2. Using the oxygen pressure condition, we fabricated top-gate GTZO-TFTs for a logic inverter, which has two serially-connected top-gate TFTs with different gate electrodes: conducting NiOx and Al. Since the electrodes have very different work functions controlling the threshold voltages of TFTs, our inverter demonstrated a nice operation at less than 5 V with a high voltage gain of over 25. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Few-layer MoS2-organic thin-film hybrid complementary inverters demonstrate a great deal of device performance with a decent voltage gain of ≈12, a few hundred pW power consumption, and 480 Hz switching speed. As fabricated on glass, this hybrid CMOS inverter operates as a light-detecting pixel as well, using a thin MoS2 channel.

On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

We report on the nanosheet-thickness effects on the performance of top-gate MoS(2) field-effect transistors (FETs), which is directly related to the MoS(2) dielectric constant. Our top-gate nanosheet FETs with 40 nm thin Al(2)O(3) displayed at least an order of magnitude higher mobility than those of bottom-gate nanosheet FETs with 285 nm thick SiO(2), benefiting from the dielectric screening by high-k Al(2)O(3). Among the top-gate devices, the single-layered FET demonstrated the highest mobility of ∼170 cm(2) V(-1) s(-1) with 90 mV dec(-1) as the smallest subthreshold swing (SS) but the double- and triple-layered FETs showed only ∼25 and ∼15 cm(2) V(-1) s(-1) respectively with the large SS of 0.5 and 1.1 V dec(-1). Such property degradation with MoS(2) thickness is attributed to its dielectric constant increase, which could rather reduce the benefits from the top-gate high-k dielectric.

We report on the fabrication of N,N'-ditridecyl-perylene-3,4:9,10-tetracarboxylic diimide-C13 (PTCDI-C13), n-channel organic thin-film transistors (OTFTs) with 30 nm Al(2)O(3) whose surface has been un-modified or modified with hexamethyldisilazane (HMDS) and thin hydrophobic CYTOP. Among all the devices, the OTFTs with CYTOP-modified dielectrics exhibit the most superior device performance and stability. The optimum post-annealing temperature for organic n-channels on CYTOP was also found to be as low as 80 °C, although the post-annealing was previously implemented at 120-140 °C for PTCDI domain growth in general. The low temperature of 80 °C hardly damages the CYTOP/n-channel organic interface which is deformed at a temperature higher than the glass transition temperature of CYTOP (∼110 °C). The pentacenequinone passivation layer turned out to be helpful to keep the interfacial trap density minimum, according to the photo-excited charge collection spectroscopy results for our 80 °C-annealed OTFTs with CYTOP-modified dielectrics.

Lead sulfide (PbS) quantum dots (QDs) have great potential in optoelectronic applications because of their desirable characteristics as a light absorber for near-infrared (NIR) photodetection. However, most PbS-based NIR photodetectors are two-terminal devices, which require an integrated pixel circuit to be practical photosensors. Here we report on PbS QD/indium gallium zinc oxide (InGaZnO, IGZO) metal oxide semiconductor hybrid phototransistors with a photodetection capability between 700 and 1400 nm, a range that neither conventional Si nor InGaAs photodetectors can cover. The new hybrid phototransistor exhibits excellent photoresponsivity of over 106 A W−1 and a specific detectivity in the order of 1013 Jones for NIR (1000 nm) light. Furthermore, we demonstrate an NIR (1300 nm) imager using photogating inverter pixels based on PbS/IGZO phototransistors at an imaging frequency of 1 Hz with a high output voltage photogain of ~4.9 V (~99%). To the best of our knowledge, this report demonstrates the first QD/metal oxide hybrid phototransistor-based flat panel NIR imager. Our hybrid approach using QD/metal oxide paves the way for the development of gate-tunable and highly sensitive flat panel NIR sensors/imagers that can be easily integrated. A hybrid near-infrared photoinverter based on lead sulphide quantum (PbS) dots and InGaZnO that exhibits a high photogain has been made. PbS quantum dots have promising properties for near-infrared detection, but two-terminal devices based on them require an integrated pixel circuit. Now, Do Kyung Hwang at Korea University of Science and Technology and co-workers have demonstrated a hybrid near-infrared detector that employs PbS quantum dots to sensitize InGaZnO. The detector covers a wavelength range of 700–1,400 nanometres, which is not covered by conventional photodetectors. It also exhibits an excellent photoresponsivity of over 106 amperes per watt. The researchers consider that this approach will open up the way to develop highly sensitive, flat-panel near-infrared sensors and imagers that are both gate tunable and readily integrable. We propose hybrid approach of two classes of PbS QD as NIR light absorber and IGZO as the photogenerated charges acceptor/transport semiconductor to create phototransistor for near infrared (NIR) detection/imaging. Such hybrid phototransistor shows photodetection capability between 700 and 1400 nm. We demonstrate a NIR (1300 nm) imager using photogating inverter pixel based on PbS/IGZO hybrid phototransistor.

Nanosheet transistors based on mechanically exfoliated MoS2 and other transition metal dichalcogenide layers have already been reported demonstrating good device performances. In an approach to synthesize a large area two-dimensional (2D) sheet, chemical vapor deposition methods were reported and the transfer of those sheets onto other arbitrary substrates was also attempted, although studies on the direct imprinting of such 2D semiconductor sheets are rare. Here, we report on a direct imprinting method, the polydimethylsiloxane (PDMS)-adopting approach, that enables the fabrication of patterned bottom-gate MoS2 nanosheet field-effect transistors (FETs) on any substrate; using direct printing methods MoS2 FETs were successfully fabricated on glass. Since our FETs were also controlled to be a depletion or an enhanced mode with the modulated MoS2 thickness on a patterned bottom-gate, our imprinting approach is regarded as a meaningful advance toward 2D nanosheet electronics.

Usually, organic thin-film transistors (TFTs) including pentacene TFTs have a bottom gate device architecture with an open back channel surface, thus requiring an ambient protecting layer on the organic devices. If the requested protecting layer has another function by chance, even more unique applications may be developed on the organic device. For such bi-functional applications, we have investigated a hydrophobic 6,13-pentacenequinone (PQ) crystalline layer on pentacene TFT for two reasons. Firstly, crystalline pentacenequinone–crystalline pentacene is quite similar to SiO2–Si structure. Because the PQ is a molecular form of already-oxidized pentacene, diffusion of water and oxygen molecules into channel pentacene may not be easy when the PQ layer is well grown on pentacene making a good PQ–pentacene interface. Moreover, the PQ protects the pentacene from high intensity ultraviolet (UV) light, since it transduces the UV into green light. After we had fabricated pentacene-based complementary photo-gating inverter devices, our inverters with the crystalline-grown PQ on pentacene channel demonstrated strong ambient-endurance preserving good inverter characteristics for 60 days under quite humid ambient air, and they also demonstrated dynamic photo-gating at a low voltage of 5 V without any UV-induced degradation.

Photoinverter and electrical-inverter applications of amorphous GaSnZnO thin-film transistors (GTZO-TFTs) with Al2O3 dielectrics were studied. The inverters were composed of two serially connected top-gate GTZO-TFTs with different gate electrodes: semitransparent conducting NiOx and opaque Al. Since the two electrodes have so different work functions as to properly arrange the respective threshold voltages of driver and load TFTs, our inverter exhibited a desirable voltage transfer characteristics with voltage gain of over 25 for electrical gating. A dynamic photogating was demonstrated with an output photogain of ∼2 V as we applied a blue illumination onto semitransparent NiOx gate, through which the photons are transmitted to excite the trapped electrons at the Al2O3 dielectric/GTZO channel interface.