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Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) $ZrO_{2}$ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ( $t_{FE}$ and $t_{IL}$ , respectively) on device performance. We observe that a decrease of $t_{FE}$ and $t_{IL}$ reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of $t_{FE}$ , $t_{IL}$ and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood.

Recently, multilevel Resistive RAM (ReRAM) stacks have been demonstrated to have promising applications related to inference and learning in artificial intelligence. However, extensive studies on energy efficiency, repeatability, and retention during multilevel operations have not been undertaken previously. It is, therefore, required to investigate the device characteristics such as compliance current (CC) dependence, forming voltage, memory window, symmetry, and switching energy. Furthermore, understanding the impact of dielectric composition and/or electrode materials is necessary to optimize the device performance, such as switching characteristics, endurance, and energy efficiency. In this work, we have investigated a two-terminal ReRAM device, 10nm Ti/50nm TiN/7nm HfO2/1nm Al2O3/PVD Ti/TiN (Fig. 1), with bilayer switching dielectrics of HfO2 and Al2O3. In this case, the embedded Al2O3 layer was placed between the HfO2 layer and the top electrode (TE). We have evaluated the gradual resistance change capability with varying CC. The I-V characteristics of the ReRAM device, measured by a dc double sweep, is shown in Fig. 2. The device switched at a compliance current of 50nA with a forming voltage of 1.85 volts to set to low resistance state (LRS) from the high resistance state (HRS). The subsequent reset from LRS to HRS was obtained during the negative voltage ramp showing a bipolar switching operation (Fig. 2). With the variation of compliance current (50 nA to 70 nA), the LRS was gradually changed indicating multilevel LRS. It is known that by increasing the compliance current with a gradual set process, multiple conducting filaments (CFs) or thicker CFs can form setting the different LRS values and the annihilation of the CFs during the reset process can also moderately vary the HRS values. The resistance ratio between the HRS and LRS was observed to be more than 1000. The devices were subjected to 100 cycles of SET and RESET operations at different CCs without any failures. When the embedded Al2O3 layer was placed between the bottom electrode (BE) and the HfO2 layer, the switching compliance current was increased to 10 mA with a reduced forming voltage of 1.6V. Multilevel LRS states were observed for this device when the CC was varied from 10 mA to 12 mA for 100 cycles at each CCs. To further understand the behavior, TEM depth profile measurements were carried out, and it was observed that Al2O3 diffused from the peak at the as-deposited location into the HfO2 layer in both cases. While this improved the uniformity in switching behavior, the low switching energy consumption in the case of an embedded Al2O3 layer in between the HfO2 layer and the TE layer remains to be investigated. Replacing the PVD Ti layer (Fig. 1) with ALD Ti in the TE when an Al2O3 layer was between the bottom electrode (BE) and the HfO2 layer reduced the switching compliance current from 10 mA to 100 nA. This suggests that the metal quality of the TE can impact the switching behavior of the multilevel ReRAMs. Figure 1

The recent discovery of ferroelectric behavior in doped hafnia-based dielectrics, attributed to a non-centrosymmetric orthorhombic phase, has potential for use in attractive applications such as negative differential capacitance field-effect-transistors (NCFET) and ferroelectric random access memory devices (FeRAM). Alloying with similar oxides like ZrO2, doping with specific elements such as Si, novel processing methods, encapsulation and annealing schemes are also some of the techniques that are being explored to target structural modifications and stabilization of the non-centrosymmetric phase. In this study, we utilized synchrotron-based x-ray diffraction in the grazing incidence in plane geometry (GIIXRD) to determine the crystalline phases in hafnia-zirconia (HZO) compositional alloys deposited by atomic layer deposition (ALD). Here we compare and contrast the structural phases and ferroelectric properties of mechanically confined HZO films in metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) structures. Both MIM and MIS structures reveals a host of reflections due to non-monoclinic phases in the d-spacing region between 1.75A to 4A. The non-monoclinic phases are believed to consist of tetragonal and orthorhombic phases. Compared to the MIS structures a suppression of the monoclinic phase in MIM structures with 50% zirconia or less was observed. The correlation of the electrical properties with the structural analysis obtained by GIIXRD highlights the importance of understanding the effects of the underlying substrate (metal vs. Si) for different target applications.

Ferroelectric and antiferroelectric Hf/Zr-based oxide films have recently gained interest for memory and AI applications due to their promise of low power and CMOS compatibility. As Hf/Zr-based oxides are not ‘new’ materials, this paper will start with an overview of past learning on this material system. Recent results on fundamental understanding of the mechanism of ferroelectric and antiferroelectric switching will be presented. Challenges in implementation of this material system in high volume manufacturing will be discussed.

Metal-insulator-metal (MIM) stacks, though simple in design, are the backbone device for resistive random access memories (ReRAM) and, as such, play a vital role in emerging memory technologies. In this work, we characterize the impact of Ar, Ar/N2, and BCl3/Cl2 plasma processes on the physical properties of the TiN bottom electrode (BE) surface. The BCl3/Cl2 process increases roughness by 40%. Ar and Ar/N2 processes both decrease PVD TiN roughness by 50%. This reduction propagates through the entire MIM stack. X-ray photoelectron spectroscopy (XPS) indicates that both plasma processes alter the Ti-ON concentration on the TiN surface. The impact of BE surface roughness and composition on MIM electrical properties is currently under investigation.

Ru capping process was demonstrated on 48nm-pitch Cu damascene interconnect with area selective deposition technique of Ru CVD. Ru nucleation and film continuity were optimized by process including wet cleaning and dry surface treatments. Physical analysis and line leakage electrical test were conducted to evaluate Ru capping layer for different process conditions.

This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- ${k}$ layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- ${k}$ layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( $ {\phi }_{\text{t1}} = {0.13}$ eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level $ {\phi }_{\text{t1}}$ (0.13 eV) was removed and $ {\phi }_{\text{t2}}$ (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, ${a}$ (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- ${k}$ layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress.

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014). S. Goley, M. K. Hudait, Materials, 2301 (2014). Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications. A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing. In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage. References Kuzum et al., Nanotechnology, 24, 382001 (2013) W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

In this Letter, we report the percentage of the ferroelectric phase in a 10-nm-thick Hf0.5Zr0.5O2 (HZO) film deposited in a metal-insulator-metal stack by atomic layer deposition. The ferroelectric behavior was confirmed by polarization measurements and piezoresponse force microscopy. Ferroelectric behavior in this material has been attributed most likely to the formation of the polar non-centrosymmetric orthorhombic phase [Muller et al., Appl. Phys. Lett. 99, 102903 (2011)], which is difficult to distinguish from the tetragonal phase in x-ray diffraction due to peak overlap. Using a model for each of the crystal phases of hafnia-zirconia, the phase percentages were estimated using a Rietveld refinement method applied to grazing incidence x-ray diffraction data and a linear combination fit analysis procedure [McBriarty et al., Phys. Status Solidi 257, 1900285 (2020)] applied to grazing incidence extended x-ray absorption fine structure data. Using these methods, it was found that the tetragonal (P42/nmc) phase is the most prevalent at 48–60% followed by the polar non-centrosymmetric orthorhombic (Pca21) phase at 35%–40% with the remainder consisting of the monoclinic (P21/c) phase. Understanding the details of the effect of the phase structure on the electrical properties of these materials is extremely important for device engineering of HZO for logic and emerging nonvolatile memory applications.

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3). References: 1) Zhao Mei et al, Journal of Semiconductors, Volume 34, No. 3, 2013. 2) A. Dimoulas et al, Appl. Phys. Lett., volume 86, no. 3, 2005. 3) Yukio Fukuda et al, IEEE transaction on electron devices, volume 57, No. 1, 2010. 4) M.N. Bhuyian et al, ECS Journal of Solid State Sci and Techn, vol. 3(5), N83, 2014. 5) C. Tian et al, J. Vac. Sci. Technol. A 24, 1421, 2006. Figure 1

For exploring the prospect of higher-k dielectric phase engineering on a high mobility substrate, films of Hf1-xZrxO2 with varying x-values (0 ≤ x ≤ 1) were deposited on Al2O3 passivated Ge substrates using atomic layer deposition (ALD) with a cyclic deposit-anneal-deposit-anneal (DADA) scheme. The evolution of monoclinic to higher-k tetragonal structure with increasing ZrO2 concentration was probed by grazing incident x-ray diffraction and partial reciprocal space maps using the highly brilliant synchrotron x-ray source at the Cornell High Energy Synchrotron Source (CHESS). A primarily amorphous/nano-crystalline matrix of the as-deposited films changed to randomly aligned grains of nanocry stalline MO2 (M=Hf, Zr) after post deposition annealing at 800 °C for 200 seconds. In contrast, the DADA films annealed for same thermal budget showed high degree of preferred orientation along certain crystallographic directions. With increasing ZrO2 content, the structure of the films changed from a monoclinic to a tetragonal phase. A lower amount of ZrO2 (x = 0.33) was required for stabilizing the tetragonal phase in films grown on Al2O3 passivated Ge substrate as compared to similar films grown on a Si substrate via the same DADA process (x ≥ 0.50).

In this paper we present an overview and examples of thin films processing technologies for future generations of leading edge semiconductor devices. We introduce the main driving forces affecting future thin film deposition and etch technologies including the push for 3D (vertical) power, performance and area scaling. We discuss new thin films processes on the near term horizon that enable future devices, improved contacts, scaled 3D interconnects, and advanced patterning technologies followed by a future outlook for scaling.

Even through Ge/high-k interface has been extensively studied the high leakage current associated with these gate stacks continues to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). Since several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are important and bulk defect and interface defect concentration affect the CV and GV characteristics several corrections to the characteristics are required to obtain accurate values. We have measured the CV and GV characteristics of Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN MOS capacitors with three different interface treatments by HP4284 LCR meter using different frequencies. The interface treatments are (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). The plots were corrected by three different methods. Firstly, we removed the effect of sheet resistance, RS . The second approach uses data (capacitance and conductance) measured at two different frequencies to solve two unknown variables (capacitance and conductance) (1). The solved CV plot is closer to the corrected CV plot at 1 MHz rather than that at 100 KHz. This allows us to use 1MHz corrected data to obtain the EOT information. Additionally, this approach helps to verify that 1MHz data is robust assuming that defects do not respond to the other frequencies used here. The third approach is to modify the measurement circuits (2) to enhance CV and GV characteristics. Fig. 1 shows the CV characteristics after the corrections by three different approaches for three different samples. COR&SPAOx samples show excellent CV characteristics. The details of all the correction methods and the advantages of these methods to correct CV and GV will be discussed. We will demonstrate that the correction methods are suitable for accurately measure the interface characteristics. The Dit calculated by two method (conductance and capacitance spectroscopy) (Fig. 2) are compared and discrepancy of the results between different samples and different methods will be explained. References Y. Ding and D. Misra, J. Vac. Sci. Technol. B, 33, 021203, 2015. K.J. Yang and C. Hu, IEEE Trans on Electron Dev, 46(7), 1500, 1999. K.S.K Kwa, S. Chattopadhyay, N.D. Jankovic, S.H. Olsen, L.S. Driscoll, and A.G. O'Neill, Semicond. Sci. Technol., 18(2), 82, 2003. Figure 1

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

As Si metal oxide semiconducting field effect transistors have continued to scale, SiO2-based gate dielectric and polySi gates have been successfully replaced by high-k dielectrics and metal gate at the 45nm technology node and beyond. In order to continue scaling, improvements of key film properties of the high-k dielectric, such as k-value and leakage current, are needed. The electrical properties of HfO2-based dielectrics may be enhanced by structural modifications, since the k-value is dependent on the crystalline phase (monoclinic k=16, tetragonal k=70 and cubic =29) [1]. HfO2 films typically crystallize into the monoclinic phase, which is its most thermodynamically stable phase [2,3]. Alloying HfO2 with other oxides such as ZrO2, TiO2, Al2O3offer a viable option towards engineering the crystalline phase. In this regards, we have deposited 40 cycles of Hf1-xAlxOy films by atomic layer deposition with Al/(Hf+Al)% ranging from 0 to 25%. A set of samples were annealed under N2 at temperatures ranging from 680 oC to 800oC and compared to the as deposited samples. To investigate the crystallinity of the films, we performed grazing incidence in-plane X-ray diffraction (GIIXRD) on the annealed films and in-situ XRD during an anneal process using synchrotron radiation was used to determine the crystallization temperature (Tc) for the unannealed films. The GIIXRD measurements revealed the presence of non-monoclinic peaks which was also confirmed by the in-situ anneal XRD measurements. The crystallization temperature of the non-monoclinic phase obtained from the in-situ anneal XRD is plotted in Fig.1, where it is shown that higher Al/(Hf+Al)% results in higher Tc. In order to resolve the non-monoclinic phase, extended X-ray absorption fine structure (EXAFS) at was utilized. The EXAFS measurement combined with GIIXRD showed the ALD Hf1-xAlxOy films crystallize into a mixture of the tetragonal and monoclinic phases. The electrical properties were investigated by MOS capacitors with ALD TiN as the metal gate. The electrical measurements show a reduction in EOT after post deposition anneal (PDA). In addition, the leakage current was also reduced by a factor of 10 while maintaining a flat-band voltage that is comparable to PDA HfO2 films under identical conditions. The C-V plots of the as deposited samples and annealed samples are shown in Fig. 2 and Fig.3 respectively. We also investigated the effect of different thermal budgets on the Hf1-xAlxOy films. A ~2Å EOT reduction with lower gate leakage was obtained for devices with post deposition anneal near the crystallization temperature of the Hf1-xAlxOyfilms. However, the electrical performance is degraded for devices with higher or lower post deposition anneal temperature than the films’ crystallization. In summary, we have successfully deposited ALD Hf1-xAlxOy. The crystal phase was confirmed to be a mixed phase of tetragonal with monoclinic. The data shows an enhancement in electrical properties near the crystallization temperature of the Hf1-xAlxOyfilms. Acknowledgements Diffraction measurements were carried out at NSLS (X20A and X20C), BNL, which is supported by the DOE, Division of Materials Sciences and Division of Chemical Sciences, under Contract No. DE-AC02-98CH10886. References [1] X. Zhao et al., Phys. Rev. B, 65, 233106 (2002). [2] E.P Gusev, V. Narayanan, M. M Frank, Phys. Status Solidi A, 201, 1443 (2004). [3] D. A Neumayer, E. Cartier, J. Appl. Phys., 90, 1801 (2001).

Use of Hf based high-k dielectric materials enabled CMOS device scaling beyond the 22 nm technology node. In order to scale the equivalent oxide thickness (EOT) to 0.7 nm and beyond, while achieving good reliability performance, improvement of the film properties and the deposition methods are highly desirable. It was observed that, the dielectric constant of ALD HfO2 can be improved by the addition of ZrO2 as it offers higher-k tetragonal stabilization when Zr/(Hf+Zr) percentage is more than 50% (1-2). It has recently been reported that the poor dielectric characteristics of ALD grown oxide films, such as the leakage current, can be improved by exposing the dielectric films to a slot-plane-antenna (SPA) plasma (3). Because of low electron temperature the SPA process causes very little damage as compared to conventional inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) plasma (4). Also cyclic treatment during the ALD deposition process by using room temperature ultraviolet ozone, D2O radical, remote microwave N2O plasma, and/or thermal annealing have shown promising results toward improving film properties (5-7). In this study, for the first time, we examined the performance benefits due to the use of intermediate SPA Ar plasma treatment (DSDS) in the ALD deposition process of Hf1-xZrxO2 with 0%, 31% and 80% Zr/(Hf+Zr) percentages and compared them with the standard deposition process (As_Dep). Zr percentage was varied by precisely controlling the Hf-precursor to Zr-precursor pulse ratio in the ALD cycle. MOSCAPs were formed with TiN as gate material, where ALD Hf1-xZrxO2 was deposited on a SiON interface formed by remote plasma radical flow nitridation of chemically grown oxide on a p-Si substrate. It is observed that, DSDS Hf1-xZrxO2with 80% Zr has the lowest dielectric thickness and interfacial layer thickness as compared to others (Fig. 1(a)). Equivalent oxide thickness (EOT) for different Zr percentages for DSDS and As-Dep processing conditions were also compared. Effect of SPA Ar plasma and Zr addition on the reliability of ALD Hf1-xZrxO2 were monitored from the flat-band voltage shift due to a constant field stress at E= 27.5 MV/cm in the gate injection mode (Fig. 1(b)). Also, the gate leakage current density, before and after stress for different devices were monitored. When subjected to a constant field stress traps are generated in the gate dielectric and at the Si-IL interface. DSDS Hf1-xZrxO2with 80% Zr showed the lowest initial flat-band voltage shift after the first 20-second stress and the subsequent increase of positive charge formation was observed as the stress continued. Devices with intermediate Ar plasma have reduced gate leakage current density before stress and after 1000s stress, which implies suppression of oxide trap formation due to plasma exposure. Intermediate Ar plasma exposure to ALD Hf1-xZrxO2with 80% Zr seems to deposit superior dielectric with better EOT downscaling ability and good reliability performance. While Zr addition helps to produce a fine grain microstructure with less oxygen vacancies (2), SPA plasma further helps by reducing contaminants, increasing mass density, and superior bond structure of the film (3). References 1. K. Tapily et al,ECS Trans., 45 (3) 411-420 (2012). 2. R.I. Hegde, et al, J. Appl. Phys. 101, 074113 (2007) 3. T. Tanimura et al, J. Appl., Phys., 113, 064102 (2013) 4. C. Tian et al, J. Vac. Sci. Technol. A 24(4), 1421(2006). 5. S. Consiglio et al, ECS Trans., 41, 89 (2011). 6. R.D. Clark et al, ECS Trans., 35(4), 815 (2011). 7. A. Delabie et al, J. Electrochem. Soc.,153, F180 (2006). Figure 1(a): Dielectric thickness (filled symbols in the left scale) for DSDS and As-Dep gate oxides and interfacial layer (IL) thickness (open symbols in the right scale) for MOSCAPs with DSDS and As-Deposited HfO2 (0% Zr), Hf1-xZrxO2 (31% Zr), and Hf1-xZrxO2 (80% Zr). (All processes used 44 ALD cycles of HfO2/Hf1-xZrxO2 deposition at 2500 C) Figure 1(b): Flat-band voltage values obtained from Capacitance-Voltage (CV) characteristics for unstressed devices (filled symbols) and after 1000s stress (open symbols) with a constant field stress at E= 27.5 MV/cm in the gate injection mode. (MOSCAPS having HfO2 (0% Zr) are denoted by squares, Hf1-xZrxO2 (31% Zr) are denoted by circles, and Hf1-xZrxO2(80% Zr) are denoted by triangles.)

Resistive random-access memory (RRAM) device has attracted wide attention for next-generation nonvolatile memory (NVM) application due to simple structure, high cycling endurance, good retention, low power consumption and fast switching time (1, 2). In recent years, RRAM devices are extensively researched for multi-level data storage (3, 4). RRAM devices can be driven to various resistance states by applying suitable compliance current values during the switching operation. In this work, multilevel resistive switching behaviors of RRAM devices with three different dielectric materials like HfO2, HfAlO2 and HfZrO2 are investigated with fixed top/bottom electrodes. To control the resistance state, a thin Al2O3 layer (1 nm) was inserted between the bottom electrode and switching dielectric (Ti/TiN/Al2O3/HfAlO2 or HfZrO2 or HfO2/Ti/TiN). The fabrication details of these devices are presented elasewhere (5). Fig. 1 shows DC endurance cycling on the LRS/HRS resistances of the three RRAM structures, (a) HfAlO2, (b) HfZrO2 and (c) HfO2 for different increasing compliance currents. The endurance cycling is performed with 20 cycles per compliance level. As can be seen from the figure, different low resistance states (LRS) and high resistance states (HRS) are well resolved after dc endurance cycling for HfAlO2 and HfZrO2 based RRAM devices. Devices with HfO2, on the other hand, does not show any multilevel LRS or HRS behavior for increase in compliance current. The reason is possibly due to the lack of oxygen vacancies available in the HfO2-RRAM structure. When HfZrO2 was subjected to a post deposition annealing (PDA) in nitrogen environment, the resistance distribution of LRS and HRS was improved, possibly due to improvement of dielectric quality while the oxygen vacancy concentration remained the same. To further improve the resistance window an additional 2 nm thick TiN layer was added before the Ti layer on top electrode of HfZrO2 based RRAM. The cycle to cycle distribution of HRS/LRS resistance of HfZrO2 based RRAM was significantly improved while the compliance current for switching was increased. In summary, process optimization and electrode selection with HfZrO2 as the switching layer can provide significant multilevel storage in RRAM devices. References: E. Ambrosi, A. Bricalli, M. Laudato and D. Ielmini, Faraday discussions DOI: 10.1039/c8fd00106e (2018). A. Prakash and H. Hwang. Physical Sciences Reviews, vol. 1(6), (2016) Chen, et al., Semiconductor Science and Technology7 (2015): 075002. J. Jang and V. Subramanian. Thin Solid Films 625 (2017): 87-92. D. Misra, S. Sultana, B. Jain, N. Bhat, K. Tapily, R.D. Clark, S. Consiglio, C.S. Wajda, and G.J. Leusink, ECS Trans., vol. 86(2), 77, 2018. Figure 1

We have integrated ALD barrier and Ru liner for novel interconnect integration and have evaluated electrical properties and time dependent dielectric breakdown (TDDB). RC and via resistance were reduced by the ALD barrier, and particularly it was confirmed that TDDB performance can be improved by using ALD TaAlN with an ultrathin film. Accordingly, ALD TaAlN barrier and CVD Ru liner are attractive barrier/liner combination for next generation interconnect integration schemes.

We have recently reported electrical performance improvements of atomic layer deposited (ALD) HfO2 films grown by use of a cyclical deposition and annealing scheme (termed DADA) compared to a single deposition with or without a post-deposition anneal (PDA). Likewise, a process for improving leakage and reliability characteristics of ALD HfZrO by use of an interspersed room temperature ultraviolet ozone (RTUVO) treatments, referred to as multi-deposition multi-room temperature annealing (MDMA), has recently been reported. We have developed a version of this MDMA process on our 300 mm clustered tool with in situ RTUVO treatments interspersed between ALD HfO2 depositions. In this report we compare these two processes (DADA vs. MDMA) for HfO2 dielectric formation in a low temperature MOSCAP flow with in-line measurements of the HfO2 and interface layer thicknesses.

Next generation CMOS devices use a high-κ dielectric layer (HfO 2 , HfSiO, HfSiON and La 2 O 3 ) grown on thin interfacial silicon dioxide as the gate dielectric. The higher dielectric constant of the Hf oxide based film stack allows a decrease in equivalent oxide thickness (EOT). Because the high-κ film stack has a greater physical thickness than an electrically equivalent SiO 2 film, the tunneling current decreases. It is a critical metrology requirement to measure the thickness of silicon dioxide and high-κ film stacks. Spectroscopic ellipsometry (SE) in the far UV wavelength region can be used to differentiate the high-κ films from silicon dioxide. This is due to the non-zero nature of the imaginary part of the dielectric function (beyond 6 eV) in the far UV region for high-κ films. There has been some conjecture that optical studies should be extended beyond 150 nm further into the VUV. This study addresses these concerns through determination of the dielectric function down to 130 nm. We show the fitted dielectric function of hafnium silicates and lanthanum oxide down to 130 nm. X-ray reflectivity (XRR) measurements were also performed on the high-κ films to complement the thickness measurements performed with SE.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

Non-volatile resistive random-access memory (RRAM) devices are currently being investigated as a low power, high density and high-speed alternative DRAM (1). A transition metal oxide dielectric layer is typically used as an insulating layer in a metal-insulator-metal (MIM) structure. To reduce the large variability of switching parameters and high operation current in these RRAM devices, bilayer dielectric structures are being explored. In this work we have used several different bilayer structures using different dielectrics. In each device the bottom electrode (BE) was 10nm Ti/50nmTiN followed by 1nm Al2O3. The second dielectric layer or the switching layer was a 7-nm HfO2 (R3), HfZrO2 (R4 with Hf:Zr%=50%) or HfAlO2 (R1 with Hf:Al%= 3%) followed by the top electrode (TE) constituting of 8nm Ti/6nm ALD TiN+50nm PVD TiN. In some cases, the top electrode was varied to 2nm ALD TiN/8nm Ti/6nm ALD TiN+50nm PVD TiN (R5) by adding a 2nm ALD TiN layer prior to 8nm Ti. Some devices with HfZrO2 (R2) were subjected to a post deposition anneal (PDA) at 700oC for 60 s. In all cases, to enhance the switching characteristics on the top electrode 8 nm Ti was used as the cap layer material except in the case of R5 where 2nm of ALD TiN was deposited prior to 8 nm of Ti. The use of thin dielectric layer of 1nm Al2O3 was to suppress the sneak-path problem (3) in the low resistance state (RON). Comparing the variation of switching layer, it was observed that the device with 1nm Al2O3/7nm HfAlO2 (R1) provided the superior average Roff/Ron values and both set and reset power compared to HfO2 (R3), and HfZrO2 (R4) devices. When the HfZrO2 (R4) devices were compared with the identical device with PDA (R2) Ron increased and Roff decreased for the PDA device, reducing the Roff/Ron value. Variation of cap layer to TiN instead of Ti also showed similar Roff/Ronbehavior. D. Ielmini, Semicond. Sci. Technol. Vol. 31, 063002, 2016. Xiaorong Chen and Jie Feng, Appl. Phys. A, vol. 120, 67 2015 U. Chand, K-C. Huang, C-Y. Huang, and T-Y. Tseng, IEEE Trans. on Electron Devices, vol. 62(11), 3665, 2015

The continued scaling of MOSFET devices necessitates the scaling of the gate dielectric in terms of equivalent oxide thickness (EOT) and associated k-value. As a replacement for SiO2 based gate dielectrics, which have reached their fundamental scaling limit, Hf-based dielectrics including HfO2, Hf silicate and nitrided Hf silicate have been chosen as viable materials.[1] Though the HfO2-based materials have generally been preferred, recent studies have shown that HfO2 with an admixture of ZrO2, which are both fully miscible, has the potential to provide a higher dielectric constant by means of stabilization of higher-k phases.[2,3] Moreover, the mixed oxide HfxZr1-xO2 has been shown to exhibit improved device performance and reliability compared to HfO2.[4] For the deposition of ultra-thin high-k gate dielectric films on planar structures, chemical vapor deposition may offer advantages in terms of wafer throughput, manufacturability, cost of ownership, and process flexibility compared to the alternately pursued atomic layer deposition based approaches. In this study we investigated the process characteristics and film properties of HfZrO4 (HfO2:ZrO2=1) thin films deposited using metallorganic chemical vapor deposition on a 300 mm production-worthy deposition chamber. The mixed oxide films were deposited using a mixture of Hf-t-butoxide and Zr-t-butoxide (1:1 molar ratio) at a wafer temperature of either 380°C or 480°C using O2 as a co-reactant. The Si wafers had a thin (~8A) layer of chemically grown SiO2. The physical properties of the films were analyzed using various characterization techniques including spectroscopic ellipsometry, corona-oxide-semiconductor (Quantox) leakage measurements, XRR, angle-resolved XPS, RBS, ICP-AES, and TEM. MOS capacitor structures featuring HfZrO4 dielectric were fabricated and tested using C-V and I-V measurements. Key electrical parameters (EOT, leakage current density, VFB) were compared with structures featuring HfO2 deposited using the same deposition system and process conditions used for the HfZrO4 process. The HfZrO4 growth rate (Fig.1) was observed to be the same for both deposition temperatures, thus indicating a mass transport limited growth rate regime. Density was observed to increase with deposition temperature in line with reported values for ALD-deposited HfZrO4 from metal chloride sources.[3] The increase in film density (and possibly decrease in film impurities) is also corroborated by improved Quantox measured leakage (Fig.2) as well as increase in metal coverage rates (Fig.3). Improvements in Jg vs EOT trends were observed when comparing HfZrO4 with HfO2 in MOS capacitor structures. Additionally, no measurable difference in CV hysteresis was observed for HfZrO4 compared to HfO2. In our deposition system an excellent wafer-to-wafer repeatability (0.86%) was observed for a mean thickness of 19 A over a 50 wafer run. These results indicate that MOCVD HfZrO4 is a promising material for advanced high-k applications. Figure 1. XRR measured thickness values and densities for HfZrO4 films deposited at 380°C and 480°C and associated growth rates determined from linear fits.

Material interactions in advanced high-κ / metal gate stacks can have a significant effect of the performance of completed devices. The effect of these interactions was investigated using planar MOS capacitor stacks that might be used for the gate of a MOS transistor. Gate electrode materials included TaN, TaSiN, and W, and HfSiO and HfSiON were used as the gate dielectric materials with an ultra-thin SiO2 interface between the silicon substrate and the dielectric. Deposition methods included CVD and ALD.

Resistance capacitance time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study, the authors report on ultrathin (∼3 nm) chemical vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, the authors determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. The authors utilized synchrotron x-ray diffraction with in situ rapid thermal an...

Electromigration and stress migration in Al metallization are major reliability issues for advanced IC's. Recently it has been shown that, compared to AlSiCu alloy films, alloys containing Si, V and Pd combine excellent plasma etchability with good corrosion resistance, while a high resistance against electromigration is maintained [1]. It is commonly accepted that the resistance against stress migration, i.e. the creep strength, of Al can be improved by addition of alloying elements in combination with appropriate heat treatments (e.g. precipitation hardening). We present data on the influence of alloying elements on the behaviour of stress as a function of temperature for a number of Al-alloy films. Pure mono- and polycrystalline Al, AlSi(1.0 at%)Cu(1.0 at%) and AlV(0.1 at%)Pd(0.1 at%) films were studied. The sputter conditions, the film thickness and the annealing conditions were similar to reliability tests described in the literature. These films are subjected to thermal cycles from 50 to 425°C in a vacuum furnace, while the stress behaviour was measured by means of wafer curvature measurements.

Using a five-step atomic layer deposition (ALD)-anneal (DADA) process, with 20 ALD cycles of metalorganic precursors followed by 40 s of rapid thermal annealing at 1073 K, we have developed highly crystalline Hf1−xZrxO2 (0 ≤ x ≤ 1) thin films (

As device feature sizes have continued to scale, new device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations in reducing short channel effects and improved performance are through the introduction of FinFETs, nanowires, and high mobility channel materials. High mobility channel materials, such as Ge and III-V (InGaAs, GaAs), are attracting increasing interest due to the possibility of realizing increased performance even without scaling the gate length of the device (1-3). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing compatibility. In this paper we report progress in high-k phase engineering through HfO2:ZrO2 doping combined with intermittent annealing and post deposition microwave plasma oxidation in order to achieve sub nm EOT with reasonable leakage. In this regard, 300mm epi Ge/Al2O3/ZrO2/TiN MOSCAP devices were fabricated using epitaxially grown Ge. We have utilized a TEL CertasTM Chemical Oxide Removal (COR) process (4), which uses anhydrous HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. The high-k stack Al2O3/HfxZr1-xO2 were deposited by atomic layer deposition on a TEL Triase +TM tool. The ALD HfxZr1-xO2 films were deposited using a cyclical deposition and annealing scheme (termed DADA) (5-6). Prior to the ALD HfxZr1-xO2 a thin ALD Al2O3 was deposited. An additional post microwave plasma oxidation was also carried out in situ. A post plasma Al2O3/ZrO2control sample with no DADA process was also fabricated. Figure 1 shows electrical leakage Jg vs equivalent oxide thickness (EOT). The electrical analysis show a scaled EOT of ~0.6nm with the combination of DADA and post plasma oxidation compared to the control sample with only post plasma oxidation processed, see Fig.1. In addition, DADA processed samples without additional post plasma oxidation (6) resulted in very high leakage. The impact of post plasma oxidation and DADA on the electrical and physical characteristics of the Hf based dielectrics will be discussed in detail. References 1.S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). 2.L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). 3. C.H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014) 4.T. Sugawara, S. Matsuyama, M. Sasaki, T. Nakanishi, S. Murakawa, J. Katsuki, S. Ozaki, Y. Tada, T. Ohta, N. Yamamoto, Jpn. J. Appl. Phys., 44, 1232 (2005). 5. K.Tapily, S. Consiglio, R.D Clark, R. Vasic, E. Bersch, J. Jordan-Sweet, I. Wells, G. Leusink, ECS Trans. 45, 411 (2012). 6. Sonal Dey, Kandabara Tapily, Steven Consiglio, Kai-Hung Yu, Robert D. Clark, Cory S. Wajda, Gert J. Leusink, Arthur R. Woll and Alain C. Diebold (2016). Higher k Tetragonal Phase Stabilization in Atomic Layer Deposited Hf1-xZrxO2 (0 Figure 1

In this study, the authors investigated atomic layer deposition (ALD) of B2O3 and BN for conformal, ultrashallow B doping applications and compared the effect of dopant-containing overlayers on sheet resistance (Rs) and B profiles for both types of films subjected to a drive-in thermal anneal. For the deposition of B2O3, tris(dimethylamido)borane and O3 were used as coreactants and for the deposition of BN, BCl3 and NH3 were used as coreactants. Due to the extreme air instability of B2O3 films, physical analysis was performed on B2O3 films, which were capped in-situ with ∼30 A ALD grown Al2O3 layers. For the BN films, in-situ ALD grown Si3N4 capping layers (∼30 A) were used for comparison. From spectroscopic ellipsometry, a thickness decrease was observed after 1000 °C, 30 s anneal for the B2O3 containing stack with 60 ALD cycles of B2O3, whereas the BN containing stacks showed negligible thickness decrease after the annealing step, regardless of the number of BN cycles tested. The postanneal reduction in...

This work investigates the interface state density, Dit by conductance method for two different processing conditions: (1) cyclic deposition and slot-plane-antenna (SPA) Ar plasma exposure, DSDS, and (2) cyclic deposition and annealing, DADA, during the deposition of ALD Hf1-xZrxO2 to fabricate the TiN/Hf1-xZrxO2/SiON/Si gate stack. The Zr percentage was varied in the dielectrics from x = 0 to 0.31 and 0.8 for DSDS processing and x = 0 to 0.8 for DADA processing. The control samples were deposited with standard atomic layer deposition (ALD) process (As-Dep) without any cyclic treatment. The addition of ZrO2 and SPA plasma exposure is found to suppress interface state generation. DSDS Hf1-xZrxO2 with x = 0.8 demonstrated superior equivalent oxide thickness downscaling and the lowest Dit. The electron affinity variation of Hf and Zr ion seems to contribute to reduced Dit generation after a constant voltage stress. On the other hand, DADA process increases the midgap Dit when Zr is added to HfO2. In addition...

Very thin amorphous W0.7Ge0.3 films have been deposited on silicon substrates by a novel chemical vapour deposition process. For films with a thickness (d) smaller than 10 nm, the observed increase of the resistivity with decreasing film thickness is well described by percolation theory. When d >10 nm, the resistivity is independent of the film thickness ( ϱ 0 =191 μΩ cm ). The superconducting transition temperature (Tc) of thick films (d >95 nm) is 4.9 K. The observed reduction of Tc with decreasing film thickness (d 95 nm) compare very well with the result obtained by Kondo for 500 nm thick amorphous W0.7Ge0.3 films made by sputtering. For the application of amorphous W0.7Ge0.3 films in submicron superconducting devices, the excellent conformal growth of CVD films might be an important advantage.

In this paper we present in situ measurements of the wafer curvature during nucleation and growth of W films deposited by chemical vapour deposition (CVD) on Si substrates. Because of the absence of stress relaxation mechanisms in the films, these measurements directly reflect the growth stress in the W films. The growth stress development is measured during self-limiting W film growth by the Si(100) reduction of WF6 and during continuous W film growth by the H2, SiH4, and GeH4 reduction of WF6. It is shown that these measurements provide detailed information on the growth kinetics (for the Si reduction of WF6) as well as the (high) growth stresses themselves. High stress gradients are observed in the growth direction of the films. In general the growth stresses range from highly tensile during the initial stages of growth, to compressive in an intermediate region and tensile again in the thick film regime. The average film stress decreases with increasing deposition temperature. The process-dependent growth stresses reported in this paper can be used to engineer the magnitude of the average film stress in W CVD metallization of integrated circuits.

A method for the in situ measurement of mechanical stress in thin films deposited in a vacuum system is presented. The bending of the substrate, a measure for mechanical stress in the deposited layer, is detected by reflecting two parallel laser beams off the surface of the substrate and measuring the angle between the two reflected beams. A hollow mirror in the path of the reflected beams acts as an ‘‘optical cantilever’’ and increases the sensitivity of this method. In the present setup it is possible to detect the difference between a flat substrate and a substrate with a radius of curvature of 6.5 km.

Spectroscopic ellipsometry (SE) with VUV wavelength region has been used to characterize high‐k films grown on SiO2/Si. The high‐k stack thickness measurements by SE are compared to thickness measurements derived from angle resolved x‐ray photoemission spectroscopy. The optical properties of hafnium silicate change with silicate concentration, which is the mechanism for SE to measure this quantity. Other factors that affect high‐k optical properties such as N concentration and annealing are also investigated.

Ultra-thin amorphous WGex layers were deposited by the GeH4 reduction of WF6. In-situ reflection measurements, resistance and RBS measurements consistently showed that a closed film is formed at a thickness of about 3 nm and that subsequent growth occurs layer-by-layer with a constant growth rate. From the measured time-dependent layer thickness, reflectivity and resistivity during the growth of the 3 nm thin film it is speculated the growth starts by nucleation and growth of WGex islands. In contrast to films deposited by the H2 reduction of WF6 the Si substrate is not consumed during the GeH4 reduction of WF6. Preliminary results indicate this is caused by a Ge layer which is formed during the initial stage of the growth. In comparison with other W-LPCVD processes the GeH4 reduction of WF6 is extremely reproducible.

The continuous scaling of Cu interconnects for sub-10nm technology nodes calls for development of ultrathin and conformal Cu diffusion barriers. Due to its ability to conformally deposit films with nanoscale thickness control, atomic layer deposition (ALD) is an attractive method for depositing refractory metal nitride diffusion barrier layers, as opposed to a line-of-sight technique such as physical vapor deposition (PVD).[1] In this regard we have previously demonstrated extendability of Cu fill (with Ru seed layer) below 25 nm linewidth (200 nm height) when PVD TaN is replaced with ALD TaN.[2] In 40 nm Cu dual damascene structures with 3 nm barrier layers, ALD TaN has also been shown to reduce via resistance by ~28% compared to PVD TaN in spite of 20x lower blanket resistivity for PVD TaN.[3] In order to further improve ALD grown TaN and minimize Cu-diffusion through these ultrathin barrier films, it is desirable to avoid forming polycrystalline films with inherent grain boundary diffusion pathways. Accordingly, alloying refractory transition metal nitrides with a third element (as for example Al) may offer a promising method for maintaining metastable amorphous films by interrupting the typical polycrystalline phase formation.[4,5] In this study, ultrathin TaN and ternary Ta1-xAlxNy films (denoted TaAlN) were deposited by ALD using metallorganic precursors and were evaluated for their effectiveness in Cu diffusion barrier applications compared to a PVD grown TaN control. TaN was deposited using tert-butylimido tris(ethylmethylamido)tantalum (TBTEMT, Ta(NCMe3)(NEtMe)3) and NH3 at 350 °C with a growth per cycle (GPC) of ~ 0.7 Å/cycle. ALD TaAlN ternary alloy films were deposited by addition of trimethylaluminum/NH3 cycles to the TBTEMT/NH3cycles using Ta:Al cycle ratios in the range 16:1 to 2:1, resulting in Al/(Al+Ta)% in the range of 21% to 88%. The effectiveness of the barrier layers against Cu-diffusion in advanced interconnects were investigated using in-situ ramp anneal synchrotron x-ray diffraction (XRD) [6,7] to study the effect of annealing on Cu diffusion with the presence of these ultrathin (~1.8 nm) barrier layers interposed between 50 nm PVD grown Cu and the Si substrate. The barrier failure temperature (Tc) was determined based on the onset of Cu3Si XRD peaks during the in-situ ramp anneal. The kinetics of Cu3Si formation was assessed by XRD using multiple ramp anneal rates and performing a Kissinger-like analysis [6] to determine the effective activation energy (Ea) for silicidation in presence of the Cu diffusion barrier layers. Compared to the film stack with PVD TaN barrier, the stacks with ALD TaN and TaAlN (Ta:Al = 8:1) exhibit a slightly higher Tc for Cu silicidation. The effective activation energy of Cu3Si formation for stacks with ALD TaN (Ea ~ 1.5 eV) and TaAlN (Ea ~ 1.3 eV) are close to the reported value for grain boundary diffusion of Cu (1.3 eV) [8], whereas the Cu3Si effective activation energy for the stack with PVD TaN (Ea ~ 2.3 eV) is closer to the reported value for lattice diffusion (2.7 eV).[8] Although the temperature of Cu3Si crystallization and corresponding barrier failure temperature is higher for these ALD barrier films compared to the PVD barrier TaN film, the failure mechanism for the ALD barriers is most likely dominated by grain boundary diffusion whereas the initial failure mechanism for the PVD barrier may be dominated by lattice diffusion. References [1] H. Kim, S-H. Kim, and H.-B.-R. Lee, Atomic Layer Deposition for Semiconductors, C. S. Hwang. Ed.; Springer, New York, 2014; pp. 209-210. [2] K. Yu, T. Hasegawa, M. Oie, F. Amano, S. Consiglio, C. Wajda, K. Maekawa, and G. Leusink, Proceedings of 2014 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 117 (2014). [3] O. van der Straten, X. Zhang, K. Motoyama, C. Penny, J. Maniscalco, and S. Knupp, ECS Trans., 64(9), 117 (2014). [4] M.-A. Nicolet, Appl. Surf. Sci., 91, 269 (1995). [5] M.-A. Nicolet and P.H. Giauque, Micro. Eng., 55, 357 (2001). [6] W. Knaepen, C. Detavernier, R.L. Van Meirhaeghe, J. Jordan Sweet, and C. Lavoie, Thin Solid Films, 516, 4946 (2008). [7] G. Rampelberg, K. Devloo-Casier, D. Deduytsche, M. Schaekers, N. Blasco, and C. Detavernier, App. Phys. Lett., 102, 111910 (2013). [8] T. Oku, E. Kawakami, M. Uekubo, K. Takahiro, S. Yamaguchi, and M. Murakami, Appl. Surf. Sci., 99, 265 (1996). Figure 1

In this study, the authors examined the effects of different annealing schemes on crystallinity in atomic layer deposition (ALD) grown Ti-containing metal gates and ultrathin ALD HfO2 high-k dielectric layers, and corresponding electrical results in metal oxide semiconductor capacitor (MOSCAP) devices. The authors investigated the effect of a postmetal deposition anneal (PMA) on the underlying HfO2, which was deposited using either a standard ALD process or a process which utilized a cyclical deposition and annealing scheme (termed DADA). The effect of the starting substrate surface, either chemically grown SiO2 or H-terminated Si, on HfO2 crystallinity was also studied. For 40 cycle ALD HfO2 (∼32 A) with a TiN overlayer, a transition from an amorphous state to a cubic phase was observed with the application of a PMA treatment. Evidence of the orthorhombic phase of HfO2 with some level of texturing was observed for 40 cycle DADA processed films annealed with a TiN cap. Concomitantly a cubic (111) texture was observed for TiN deposited on DADA processed HfO2 and subjected to a PMA. Suppression of crystallinity for HfO2 deposited on H-terminated Si and annealed with a TiN layer was observed which illustrates the need for an adequate nucleation layer for uniform grain growth and increased atomic ordering. The authors also investigated metal gate stacks with a bilayer of TiN overlying Ti which showed reflections from both cubic TiN and hexagonal TiN0.3 in the as-deposited state and after annealing clear evidence of silicidation (TiSix) was observed. In MOSCAP structures with 40 cycle ALD HfO2 and a TiN overlayer subjected to a PMA, although the cubic phase of HfO2 was stabilized, there was no associated improvement in device scaling. This study highlights the importance of the initial crystalline state and nucleation of HfO2 as well as the thermal stability of the capping metal layer material when engineering dielectric layer crystallinity by means of a postmetal cap anneal. For ultrathin HfO2 integrated in advanced metal oxide semiconductor structures, the benefits of the stabilization of a higher-k phase through postmetal gate anneal may not be fully realized due to increased leakage along grain boundaries or decrease in effective k due to changes in the lower-k interfacial layer.

As Si Metal Oxide Semiconducting Field Effect Transistors (MOSFETs) have continued to scale Short Channel Effects (SCE) have become exacerbated by the inability to continue scaling the Equivalent Oxide Thickness (EOT) of the device significantly beyond what was realized with the introduction of High K Metal Gate (HKMG) MOSFETs at the 45nm technology node. Since EOT scaling has not kept pace with the gate length (Lg) scaling needed to continually increase the transistor drive current, device makers have instead elected to introduce FinFET and Tri-Gate transistors with inherently better electrostatic control in order to realize reasonable SCE in the device. High mobility channel materials, such as Ge, are attracting increasing interest due to the possibility of realizing increased performance even without scaling the Lg of the device (1). Ge is particularly attractive for use as a channel material for P-type MOSFETs (PMOSFETs) due to its high hole mobility and Si processing compatibility. In fact, we have demonstrated experimental PMOSFET devices with hole mobilities significantly higher than what can be obtained on Si, Fig. 1. However, a significant remaining challenge to incorporating Ge into VLSI production is obtaining a stable and well-passivated dielectric/semiconductor interface using tooling and substrates compatible with current 300mm Si VLSI High Volume Manufacturing (HVM) in order to achieve reasonable device performance at sub 1nm EOTs (2). In this paper we will report progress on surface passivation and functionalization of Ge channel surfaces, as well as High K dielectric layer growth by Atomic Layer Deposition (ALD) and the resulting electrical properties measured by fabricated MOSFETs and Metal Oxide Semiconducting Capacitors (MOSCAPs). The Ge channel devices were formed on 300 mm Si wafers using Ge grown by an epitaxial process including a graded SiGe buffer layer. We have utilized a TEL CertasTMChemical Oxide Removal (COR) process (3), which uses dry HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. We have also studied Ge oxide interface layer formation by plasma oxidation using a Slot Plane Array (SPA) antenna (4) utilizing in-line X-ray Photoelectron Spectroscopy (XPS) to measure Ge and high K oxide thickness on monitor wafers fashioned by the same Ge epitaxial process used to make the electrical devices and compared it to the equivalent Si oxidation process, Fig. 2. Various other passivation and interface schemes were investigated and will be discussed, contrasted and compared including ozone oxidation, Al oxide passivation/interface layers, SPA plasma nitridation, and thin amorphous Si passivation layers. We have utilized Hf oxide grown by a previously reported ALD process (5) as the High K dielectric for our devices, and TiN as the metal gate. Our results show that Ge channel devices can be fabricated on 300mm Si substrates using Si VLSI-compatible toolsets and infrastructure and resulting in reasonable device characteristics, Fig. 3. Thus, Ge channel MOSFETs are found to be a promising technology for use in HVM at future VLSI technology nodes. References 1. S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). 2. L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). 3. T. Hamelin, J. Wallace, and A. LaFlamme, U.S. Patent No. 7029536. 4. T. Sugawara, S. Matsuyama, M. Sasaki, T. Nakanishi, S. Murakawa, J. Katsuki, S. Ozaki, Y. Tada, T. Ohta, N. Yamamoto, Jpn. J. Appl. Phys., 44, 1232 (2005). 5. R.D. Clark, S. Consiglio, C. Wajda, G. Leusink, T. Sugawara, H. Nakabayashi, H. Jagannathan, L.F. Edge, P. Jamison, V. Paruchuri, R. Iijima, M. Takayanagi, B. Linder, J. Bruley, M. Copel, V. Narayanan, ECS Trans. 16, 4, 291 (2008)

A multi-technique approach was used to determine the crystalline phase, texture, and electronic structure of Hf1−xZrxO2 (x = 0–1) high-k gate dielectric thin films grown by atomic layer deposition using a cyclical deposition and annealing method. X-ray diffraction (XRD) analysis performed in both grazing incidence and pole figure configurations identified the tetragonal phase for Zr/(Zr + Hf)% = 58% and a concomitant increase in tetragonal phase for further increase in Zr content. X-ray absorption spectroscopy (XAS) was used to determine the local atomic structure and metal oxide bond orientation. Polarization dependent XAS in normal and grazing incidence showed preferential metal-oxygen bond orientation consistent with the texturing observed by XRD. X-ray photoemission spectroscopy (XPS) and spectroscopic ellipsometry (SE) were also performed with special focus on spectral features which arise as a consequence of atomic ordering and specific crystalline phase. The combination of XAS, XPS, SE, and XRD enabled the determination of the effects of the deposition scheme and compositional alloying on the electronic structure, crystal field effects, optical properties, crystal phase, and texture for the mixed oxide alloy series. The multi-technique approach revealed the martensitic-like transformation of crystalline phase from monoclinic to tetragonal as the majority metal oxide concentration in the alloy mixture changed from HfO2 to ZrO2.

In order to enhance the dielectric properties of HfO2, the alloying of HfO2 with ZrO2 was studied. HfxZr1-xO2 films with different Hf:Zr ratios were deposited by atomic layer deposition (ALD) combined with a cyclical deposition and annealing scheme (termed DADA) in which an annealing was performed after every 20 ALD cycles. The impact of the ZrO2 addition on the structural properties of the ALD grown films was investigated by grazing incidence in-plane X-ray diffraction and pole figure measurement using synchrotron radiation as well as transmission electron microscopy and X-ray photoelectron spectroscopy. The HfxZr1-xO2 films with x=1 show the presence of monoclinic (-111) fiber texture. As the Zr content increases, stabilization of the tetragonal phase is observed. The pole figure measurements indicate the presence of tetragonal (111) fiber texture for the ALD HfxZr1-xO2 films with higher Zr content grown by DADA in contrast to random orientation in post deposition annealed films.

For the purpose of extending the upper temperature limit of metallorganic atomic layer deposition, mixed ligand precursors containing cyclopentadienyl (Cp, C5H5) ligands have been shown to exhibitsuperior thermal stability compared to the widely adopted tetrakis(ethylmethylamino)hafnium (TEMAH) precursor while also possessing adequate vapor pressure characteristics for use in atomic layer deposition (ALD) processing. In order to prevent the deleterious oxidation of the underlying Si from O3 the use of a milder oxidant such as H2O is preferred. Accordingly in this study, we investigated ALD using the liquid precursors CpHf(NMe2)3 and (CpMe)2Hf(OMe)Me in the temperature range 305 – 410 °C with H2O as a co-reactant and compared the film growth and electrical properties with films deposited using a conventional TEMAH/H2O process at 305 °C as well as the same process with an optimized annealing scheme. The CpHf(NMe2)3/H2O process was observed toexhibit a growth-per-cycle (GPC) in the range 0.23 – 0.36 A/cycle ...

We have recently reported electrical performance improvements in atomic layer deposited (ALD) HfO2 films grown by use of a cyclical deposition and annealing scheme (termed DADA) compared to a single deposition followed by a post-deposition anneal (PDA). We previously proposed a model for bottom-up crystallization in DADA films in contrast to random crystallization for PDA films. To elucidate the mechanisms for this structural modification, in this study we utilized grazing incidence in-plane X-ray diffraction and pole figure measurements using synchrotron radiation as well as transmission electron microscopy. Structural differences were investigated from different annealing conditions as well as from different thickness of films. We observed significant differences in structural properties of DADA films compared to films receiving PDA. We also report on the evolution of monoclinic HfO2 with a (-111) preferred orientation (fiber texture) for DADA films whereas PDA treatment resulted in a random grain alignment and mixed phase structure.

We present both EOT scaling and flatband voltage (Vfb) shift for Hf-based high-k containing metal-oxide-semiconductor capacitors (MOSCAPs) due to Al addition into the TiN metal gate. The metal gate was deposited using chemical vapor deposition (CVD) and the Hf-based high-k films were deposited using CVD or atomic layer deposition (ALD) in 300nm deposition chambers. We found that the Vfb shift amount by Al addition into TiN depends on the high-k film (HfO2 vs. HfSiON) as the shift for the HfO2 containing stack was greater than that in the HfSiON containing stack. We also examined the effect of the thermal budget of the MOSCAP flow on the Vfb shift by Al addition into TiN. We observed that the Vfb shift direction by Al addition into TiN was dependant on the MOSCAP flow (gate-first vs. gate-last like) and this Vfb shift behavior can be explained by Al-based dipole and oxygen vacancy models.

With the replacement of SiO2 by high-k Hf-based dielectrics in complementary metal–oxide–semiconductor technology, the measurement of the high-k oxide bandgap is a high priority. Spectroscopic ellipsometry (SE) is one of the methods to measure the bandgap, but it is prone to ambiguity because there are several methods that can be used to extract a bandgap value. This paper describes seven methods of determining the bandgap of HfO2 using SE. Five of these methods are based on direct data inversion (point-by-point fitting) combined with a linear extrapolation, while two of the methods involve a dispersion model-based bandgap extraction. The authors performed all of these methods on a single set of data from a 40 A HfO2 film, as well as on data from 20 and 30 A HfO2 films. It was observed that the bandgap values for the 40 A film vary by 0.69 eV. In comparing these methods, the reasons for this variation are discussed. The authors also observed that, for each of these methods, there was a trend of increasing...

In this work we present physical and electrical characterization of HfO2 films deposited using the Dep-Anneal-Dep-Anneal (DADA) deposition scheme. Electrical results from MOSCAP devices fabricated using a low temperature (Gate Last-like) integration flow are presented. In addition we report detailed physical analyses of the films and changes in the films versus as-deposited ALD HfO2 and films undergoing a single post-deposition anneal and show the correlation between observed physical changes in the film and electrical results. Observed physical changes using HR-RBS, HR-TEM, SIMS, XPS and XRR include crystallization, densification, Si intermixing, reduction of in-film carbon and improved etch resistance leading to improved leakage vs. EOT and electrical non-uniformity. Dependence of these changes on the underlying interface layer (e.g. SiO2 vs SiON) is also described.

The influence of temperature gradients on the partial pressures of a binary mixture in a cold wall low pressure chemical vapor deposition reactor was determined by Raman spectroscopy of the gaseous species in the reactor. It is demonstrated for the first time that the partial pressure of the heavy constituent in the hot region of a low pressure reactor is reduced by 35 % due to the Soret effect. Model calculations that included the Soret effect are in agreement with the experimental data.