1. Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process
- Author
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Christopher J. Jezewski, Kanwal Jit Singh, Florian Gstrein, Robert B. Turkot, Richard E. Schenker, Rohan Akolkar, Jasmeet S. Chawla, Ramanan V. Chebiam, Hui Jae Yoo, M. Harmes, Gary Allen, James S. Clarke, Colin T. Carver, B. Krist, Hazel Lang, Tejaswi K. Indukuri, and Alan Myers
- Subjects
Interconnection ,Materials science ,business.industry ,Process (computing) ,chemistry.chemical_element ,Dielectric ,Copper ,chemistry ,Distortion ,Electronic engineering ,Optoelectronics ,Electrical measurements ,business ,Lithography ,Next-generation lithography - Abstract
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.
- Published
- 2013
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