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We show how a CD-TEM (Critical Dimension-Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming. In addition, we demonstrate how detector shadowing can be reduced significantly by using a special specimen holder and modified grids. The recipe, which runs autonomously and automatically, is verified using examples from modern FinFET and non-volatile memory devices.

We show how a CD-TEM (Critical Dimension- Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming.

This paper discusses the Failure Analysis methodology used to characterize 3D bonded wafers during the different stages of optimization of the bonding process. A combination of different state-of-the-art techniques were employed to characterize the 3D patterned and unpatterned bonded wafers. These include Confocal Scanning Acoustic Microscopy (CSAM) to determine the existence of voids, Atomic Force Microscopy (AFM) to determine the roughness of the films on the wafers, and the Double Cantilever Beam Test to determine the interfacial strength. Focused Ion Beam (FIB) was used to determine the alignment offset in the patterns. The interface was characterized by Auger Spectroscopy and the precession electron nanobeam diffraction analysis to understand the Cu grain boundary formation.

Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.

A novel copper electroplating and CMP process was developed to effectively modulate the within-wafer and within-die nanoscale topography. The feasibility of this new metallization is demonstrated on a 64nm pitch product with an equivalent defect level, lower and tighter distribution in resistance and trench height. It's believed to be extendable to other advanced nodes for a sizable reduction in copper overburden which saves CMP polish cycle time from the plan-of-record time.

Electromigration and resistivity of Cu, Co and Ru on-chip interconnections have been investigated. Non-linered Co and Ru interconnects can have better interconnect resistance than Cu, if the Cu liner cannot be scaled down below 2 nm in future interconnect technologies. A similar resistivity size effect increase was observed in Cu, Co, and Ru. Multi-level Cu, Co or Ru back-end-of-line interconnects were fabricated using 7 and 10 nm node technology wafer processing steps. EM in 18 nm to 88 nm wide Co lines, 18–24 nm wide Cu with a thin Co cap and 18 to 24 nm wide Ru lines were tested. The electromigration activation energies for Cu with Co cap, Co and Ru were found to be 1.5–1.7 eV, 2.4–3.1 eV and 1.9 eV, respectively. These data showed that Cu with Co cap, Co and Ru interconnects all had highly reliable electromigration.

Display Omitted The evolution of CMOS technologies and of the silicidations techniques are described.A peculiar nickel monosilicide defect termed NiSi-Fang is detected and characterized.The NiSiGe formation is investigated on Si, SiGe materials and (100), (111) surfaces.A mechanism for the NiSi-Fang defect formation is proposed.This mechanism involves silicide formation, metal enrichment and metal diffusion. In this paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g. SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. We also investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (100) and (111) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni-Pt-Si-Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

Experimental decomposition of contributions of electron scattering events in deeply scaled interconnects has been complicated by the fact that grain size and line dimensions are generally not varied independently. In this paper, we describe a combination of experiments to examine scattering mechanism independently. The cross section of was changed by recessing individual copper interconnects from the top using wet chemical etching, which was combined with repeated cryogenic resistance measurements. A fit for the grain boundary reflectivity was then obtained. In addition, it was found that the average grain size increase from the bottom to the top of the interconnect. This was confirmed by TEM based grain size measurements. Further, in order to assess surface scattering, magnetoresistance was employed for the first time for interconnects. It is observed to be sensitive to the geometry of the line. The method also allows for independent assessment of sidewall vs. bottom/top surface scattering. Results indicate that sidewall scattering is more severe than top/bottom surface scattering.

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6nm.

Titanium nitride (TiN), a refractory material is actively been used as a diffusion barrier in Middle-of-the-Line (MOL) contacts. In the typical MOL stack (titanium (Ti)/TiN/tungsten(W)), it acts as a fluorine (F) diffusion barrier and also as an adhesion layer to W. During W deposition, F from W precursor chemistry can react with Ti to form a highly resistive titanium fluoride (TiFx) compound. The formation of TiFx creates >200% volume expansion which can result in cracks on the TiN layer or W delamination. In order to be an effective diffusion barrier layer, TiN has to be dense which demands a critical thickness. In this work, we study the materials properties of ALD TiN as a function of thickness in the range 11–35 Â. We found a linear increase in resistivity of TiN on Ti with thickness. Columnar structured microstructure was observed for TiN films with thickness 30.4 and 34.7 Â. These films were also found to be slightly denser. TEM electron diffraction indicated that the 34.7 Â film is preferentially oriented along [111]. The roughness of the film increases with thickness. Three roughness zones with different crystallization modes have been identified which indicates thickness dependent crystallization. From our study, it is clear that in addition to density, the formation of preferential orientation of TiN might play a role for critical thickness requirement.

An improvement in interconnect performance implies a reduction of the resistance-capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

Introduction A porous low-k film has been introduced to reduce the interconnect capacitance as the LSI generation progress [1-2]. Since the porous low-k film has larger porosity and higher carbon content than conventional rigid films, its surface is easily damaged by processes during integration. The damage layer has lower carbon concentration and hydrophilic properties, so the moisture uptakes in it [3]. The moisture uptake into porous low-k film causes the line capacitance increase [4]. In this work, we investigated the moisture uptake impact on line capacitance and leakage current in the triple layer interconnect structure. We also estimated dielectric constant of damage layer with including moisture by the capacitance simulation. The moisture control in the damage layer in porous low-k film is very important to reduce the line capacitance and improve the line leakage current as well as damage layer reduction.

Modulation of Cu interconnect microstructure in a low-k dielectric was achieved at an elevated anneal temperature of 250 °C. In contrast to the unpassivated conventional structure, a TaN metal passivation layer was deposited on the plated Cu overburden surface before annealing at the elevated temperature to prevent stress migration reliability degradation. As compared with the conventional structure annealed at 100 °C, the elevated annealing process enabled further Cu grain growth, which then resulted in an increased Cu grain size and improved electromigration resistance in the interconnects.

As the dimensions of semiconductor devices become smaller, the use of high-k materials as gate oxides has become necessary for controlling gate leakage current. In addition, to achieve higher performance, conventional polysilicon metal gates have been replaced with multistack metal electrodes with engineered work functions. Thus, a suite of devices with different levels of performance and power usage is available. The integration scheme to create such structures involves an additional deposition step and selective wet etching of titanium nitride (TiN) in a complex patterning scheme following the high-k film deposition. Tantalum nitride (TaN) is one of the candidates used as an etch stop layer in a bilayer scheme of TaN/TiN. This prevents any exposure of high-k hafnium oxide (HfO2) gate oxide to wet etch chemistry in the patterning scheme, which could cause damage and/or skimming, resulting in undesirable effects on device characteristics and reliability. In order to accommodate for shrinking trench widths, these bilayer stacks are kept as thin as possible, which makes monitoring the thickness during various patterning steps very challenging. In this study, the authors present an approach to an offline and inline metrology setup. In order to gain insight into basic layer growth and interdiffusion characteristics, they used x-ray photoelectron spectroscopy and high-resolution transmission electron microscopy. They utilized specular x-ray reflectivity as a first principles method, followed by wavelength dispersive x-ray fluorescence to gain insight into cross-wafer variation on blanket wafers. The results were then fed into models developed for the x-ray photoelectron spectroscopy technique, which can be used as an inline method to characterize the composition and thickness of the patterned wafers for both as-deposited and postetching.As the dimensions of semiconductor devices become smaller, the use of high-k materials as gate oxides has become necessary for controlling gate leakage current. In addition, to achieve higher performance, conventional polysilicon metal gates have been replaced with multistack metal electrodes with engineered work functions. Thus, a suite of devices with different levels of performance and power usage is available. The integration scheme to create such structures involves an additional deposition step and selective wet etching of titanium nitride (TiN) in a complex patterning scheme following the high-k film deposition. Tantalum nitride (TaN) is one of the candidates used as an etch stop layer in a bilayer scheme of TaN/TiN. This prevents any exposure of high-k hafnium oxide (HfO2) gate oxide to wet etch chemistry in the patterning scheme, which could cause damage and/or skimming, resulting in undesirable effects on device characteristics and reliability. In order to accommodate for shrinking trench widths...

Grain size modulation in Cu interconnects was achieved at an elevated anneal temperature of 250 °C. As compared to the conventional annealing at 100 °C, the elevated process enabled further Cu grain growth, which then resulted in an increased grain size and improved electromigration resistance in the Cu interconnects. In order to prevent stress migration reliability degradation from the elevated annealing process, a TaN metal passivation layer was deposited on the Cu interconnect surface prior to the thermal annealing process, which suppressed void formation within the Cu features during the anneal process and reduced inelastic deformation within the interconnects after cooling down to room temperature

We have combined experiments and atomistic modeling in order to better understand the growth and structure of metal films deposited onto sidewalls of trenches and vias. Using x-ray reflectance, atomic force microscopy, and high-resolution transmission electron microscopy to characterize the microstructure and morphology of Ta films grown by magnetron sputtering onto inclined substrates, we find that films deposited at larger incidence angles tend towards columnar microstructure with high roughness and low density. We have used a three-dimensional Monte Carlo model (ADEPT) to simulate the growth process, under conditions close to those investigated experimentally. A binary collision model is included in the Monte Carlo deposition procedure to describe the interaction of energetic particles with the surface. Examination of the film microstructure and morphology resulting from the simulations indicates that the energetic impinging particles are necessary to produce film densities comparable to those found ex...

We show that surface evolution resulting from the deposition of discrete particles is intrinsically different from that produced by continuum processes. The atomistic effects have major consequences, even when observed at macroscopic length scales. We have elucidated some of the atomistic effects by comparing: (i) numerical simulations of thin film deposition using the continuum model, (ii) atomistic (Monte Carlo) models, and (iii) experiments on the sputter deposition of Ta onto a substrate containing etched vias. We have therefore developed a continuum model which incorporates finite atomic length scales. The model incorporates effects of atomic interactions, which lead to the capture of impinging atoms that pass near a point on the film. This capture effect results in “breadloafing” at sharp convex corners where the curvature is high. We have validated our model in idealized two-dimensional simulations and obtained improved qualitative agreement with both experiment and Monte Carlo atomistic simulation...

We describe the reliability projection methods currently used and show that 1.6 nm oxides are sufficiently reliable even if soft breakdown is considered the point of failure. We also explore the possibility of using oxides after soft breakdown.

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical-vapor-deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by raising the deposition pressure. Degree of electromigration (EM) resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6 nm.

Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.

Metallization is the back end of the integrated-circuit (IC) fabrication process where the transistor interconnections are formed. Figure 1 shows the metallized part of a static random-access memory chip. Metal lines for electrical connections (Al and Cu) in Si devices are deposited as blanket films and then etched or polished away to define the conducting lines.

Alternating phase shift technology has been shown to substantially improve focus latitude and resolution for several years. However, the use of phase shift masks to improve the process latitude in gate level lithography has been hindered by the lack of commercially available tools that can convert conventional gate layouts into phase shift mask patterns. A software package has recently become available that allows a user to create phase shift masks to reduce the gate length of features in existing circuit layouts. A digital signal processing chip with 2 million gates has been used as a test vehicle to evaluate the feasibility of phase shifting and processing a large number of devices in a complete circuit. Three wafer lots have been processed with a target feature size of 120 nm with a variation of 25 nm 3σ. The timing circuits of the chips have been tested; those with 120 nm gates showed a nearly fourfold improvement in speed when compared to 240 nm gate circuits at 1 volt operation.

The important components of reliability projection are investigated. Acceleration parameters are obtained for a 1.6 nm oxide with a soft breakdown criterion. Based on the physical percolation model, the voltage scaling factor for time to breakdown is found to increase with lower voltage, explaining the experimental observation of 6.7 ± 0.4 dec V-1 for the 1.6 nm oxide. The distribution of breakdown times is shown to be sensitive to thickness variation across the test wafer, and a Weibull slope of 1.38 ± 0.1 was obtained. The temperature dependence of the time to breakdown was found to be non-Arrhenius and to have a slope of 0.02 dec °C-1. Using these parameters, the 1.6 nm oxide was found to have a 10 year lifetime with a 100 ppm failure rate for 1.3 V operation at 100 °C. Our understanding of soft breakdown is described as well as an investigation of device operation after soft breakdown, which may further improve the reliability projection.

To demonstrate the effectiveness of alternating aperture phase shift lithography and 193nm wavelength lithography for integrated circuit technology, two demonstration devices were designed and processed. In one case, a 2 million transistor integrated circuit was processed with phase shifting and 248nm wavelength lithography. Gate lengths were reduced from 240 to 120nm, resulting in a 100MHz circuit speed at 1.0 volt operation, a threefold improvement. In the second case an 80nm floating gate memory device was fabricated with phase shifting, 193nm wavelength lithography, and anti-reflection control. The lithographic results were confirmed by careful measurements throughout the process sequences and finally by the performance of the devices themselves.

Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage (C–V) measurements on these capacitors showed a systematic change in the accumulation capacitance when additional implant damage is introduced by a 1×1014 cm−2 40 keV silicon implant. The oxide thickness values extracted from the C–V data increase by 1–4 A with the additional implant damage. This trend is confirmed by additional high resolution TEM and X-ray reflectivity measurements. We postulate that the implant damage increased the oxidation rate, due either to the interstitial flux during TED, or to an increase in surface roughness. For channels doped with boron implantation, the increase in thickness does not change with a 5× increase in the doping dose. In contrast, with BF2-implanted channels, the effects are smaller for higher doping dose.

We demonstrate the first successful mapping of the two-dimensional electrostatic potential in semiconductor transistor structures by electron holography. Our high resolution 2D phase maps allow the delineation of the source and drain areas in deep submicron transistors. By measuring the mean inner potential of Si and surface depletion effects in thin cross-section samples, we have directly determined the 2D electrostatic potential distribution with 10 nm spatial resolution and 0.1 V sensitivity. We discuss the sensitivity limits of the technique, and outline its possible applications in the study of solid state reactions in two dimensions within a few nanometers of the surface.

In materials that have bulk inversion symmetry, optical second harmonic generation (SHG) is sensitive to regions where the inversion symmetry is broken, i.e., a surface or interface. We measure SHG from the interface between Si(100) and thin layers of SiO2. Measurements on a series vicinal samples (0°–5° off axis) show that one- and threefold symmetries in the SHG signal increase with increasing off-axis angle. Comparison to x-ray scattering measurements of the interface roughness, for a set of on-axis samples, demonstrates the sensitivity of SHG to interface roughness.

Alternate metallization schemes for copper interconnect using selective CVD Co capping at the 22nm technology node are investigated. Control splits fabricated with PVD Ta(N) barrier/liner layers and CuMn alloy seedlayers are compared against interconnects fabricated using a PVD TaN barrier/CVD Co liner scheme with selective CVD Co capping. Secondary ion mass spectroscopy (SIMS) studies of PVD TaN barrier/CVD Co liner structures indicates that top-surface segregation of the Mn-dopant in alloy seedlayers is suppressed in the presence of the CVD Co Liner. Alternate metal capping in the form of selective CVD Co layers is evaluated in combination with CVD Co liners. Good electrical yields are obtained in-line with the Co liner/Co cap scheme. The PVD TaN/Co-Liner/Selective CVD Co cap combination is seen to have greatly enhanced electromigration performance over PVD Ta(N)/PVD CuMn controls, with T50 fail times for the former being ~100x longer than the controls. Kinetics studies of the CVD Co liner/selective Co cap samples show electromigration activation energies of 1.7 eV, a substantial enhancement over the 1.0 eV obtained for the PVD Ta(N)/CuMn controls.

We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O/sub 2/ or N/sub 2/O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N/sub B/, for thicknesses other than those measured. We find that the minimum t/sub ox/ required to inhibit boron penetration is always 2-4 nm less when N/sub 2/O-grown gate oxides are used in place of O/sub 2/- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t/sub ox/, incremental variations in oxide thickness result in a large variation in N/sub B/, leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10/sup 11/ cm/sup -2/.

Cu(Mn) alloy seed BEOL studies revealed fundamental insights into Mn segregation and EM enhancement. We found a metallic-state Mn-rich Cu layer under the MnOx layer at the Cu/SiCNH cap interface, and correlated this metallic layer with additional EM enhancement. A carbonyl-based CVD-Co liner film consumed Mn, reducing its segregation and EM benefit, suggesting O-free Co liner films are strategic for Cu-alloy seed extendibility.

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6nm.

With the continuing aggressive scaling of interconnect dimensions and introduction of new lower k materials, dielectric TDDB reliability margin is greatly reduced. In this paper, a comprehensive investigation on an abnormal low-k TDDB characteristic, a systematic degradation of Weibull slopes at lower stress voltages, was conducted for Cu and CuMn alloy interconnect with porous ultra low-k (ULK) CVD dielectric (k=2.4). Based on extensive electrical and physical evidences, such abnormal TDDB characteristic was attributed to slow metallic diffusion in bulk ULK induced by Mn and Cu segregation. A new TDDB model based on invasion percolation was proposed to successfully model the observed abnormality. CuMn interconnect with robust liner to assure metal free ULK has become important for TDDB reliability.

The high current density induced failure in Ge 2 Sb 2 Te 5 (GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

A 32 nm BEOL with PVD CuMn seedlayer and conventional PVD-TaN/Ta liner was fully characterized by fundamental, integrated, and reliability methods. CuMn was confirmed to have fundamental advantages over CuAl, such as higher electromigration (EM) reliability for the same Cu line resistance (R). Both low R and high reliability (EM, SM, and TDDB) were achieved. Improved extendibility of CuMn relative to CuAl was also supported by studies of alloy interactions with advanced liner materials Ru and Co, and by enhancement of ultra-thin TaN barrier performance.

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.

We demonstrate the application of quantitative chemical lattice imaging techniques to a metallic system. The first results establish that the chemical interface between γ and γ′ phases of a nickel-based superalloy can be quantitatively identified.

We report a detailed investigation of the precipitation behavior of gold in float-zone silicon from a highly supersaturated solution. Nucleation, morphology, and crystallography as well as the decomposition of the solution were examined using high-resolution electron microscopy, selected area diffraction combined with tilting experiments, Hall-effect measurements, and energy dispersive x-ray spectroscopy. After in-diffusion of gold at 1275 {degree}C annealing experiments were performed at 850 {degree}C for durations ranging from 5 min up to 35 d. It is shown that gold precipitates in small spherical particles (diameter: 10--20 nm) consisting of a metastable gold silicide. By means of selected area diffraction combined with a special tilting procedure, the unit cell is proved to be orthorhombic with lattice parameters {ital a}=0.971 nm, {ital b}=0.768 nm, and {ital c}=0.703 nm. Systematic absence of reflections in several precipitate zone-axis patterns reveals the space group of the silicide to be {ital Pnma} or {ital Pn}2{sub 1}{ital a}. According to Hall-effect measurements the concentration of substitutional gold decreases to a few percent within 5 min annealing at 850 {degree}C. Only a part of it has precipitated in gold silicide particles, which are found at small extrinsic stacking faults. The stacking faults represent a density of self-interstitialsmore » Si{sub {ital i}} of about 10{sup 18} cm{sup {minus}3}, which according to control experiments is about a factor of 50 above the equilibrium concentration of Si{sub {ital i}} at 1274 {degree}C. As annealing proceeds the stacking faults disappear, and gold is finally found in spherical particles embedded stress-free into the silicon matrix.« less