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Nitrogen doping is introduced in elevated-metal metal-oxide (EMMO) thin-film transistors (TFTs) by sputtering amorphous indium gallium zinc oxide (a-IGZO) channel in Ar and N2 gas mixture. The electrical characteristic and reliability of TFTs under negative/positive bias illumination stress (N/PBIS) are systematically investigated on TFTs of different channel lengths (${L}\text{s}$). Compared with undoped TFTs, the short-channel effect (SCE) of the N-doped TFTs is significantly suppressed, the persistent photoconductivity (PPC) effect is weakened, and N/PBIS reliability is largely improved. Short- and long-channel N-doped TFTs have about the same reliability performance. X-ray photoelectron spectroscopy (XPS) analysis shows that N-doping forms Zn=N bonds in the channel and oxygen vacancies (${V}_{O}$) are reduced. Based on a group of TFTs with different ${L}\text{s}$ , channel mobility ($\mu _{{\mathrm {ch}}}$) and source–drain series resistance (${R}_{{\mathrm {sd}}}$) are correctly extracted. In N-doped TFTs, $\mu _{{\mathrm {ch}}}$ has a limited decrease owing to the increase in ${R}_{{\mathrm {sd}}}$. N-doped TFTs with different Ar/N2 gas-flow ratios show similar electrical and reliability performance, indicating a wide process window. [ABSTRACT FROM AUTHOR]

Degradation of flexible low-temperature poly-Si TFTs under dynamic bending stress is studied in controlled ambient of different kinds. It is demonstrated that synergistic effect of H2O vapor and O2 is the origin of the positive threshold voltage (${V}_{\text {th}}$) degradation of poly-Si TFTs under dynamic bending stress in the air ambient, while the dynamic bending stress alone does not cause any TFT degradation. The degradation is found to strongly depend on the ratio of O2 to H2O vapor in the ambient. A degradation model of “H2O and O2 assisted electron transport and capture” is proposed, which is based on the participation of both reactants in reactions with dangling bonds along the micro-/nano- cracks penetrating through the passivation layer into the active region of TFTs, formed under the dynamic bending stress. [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) severely degrade under AC gate bias stress and AC drain bias stress, whose transfer curves respectively undergo positive shifts of 6.3 and 14.2 V after a stress time of 3000 s with a stress amplitude of 20 V. In this study, annealing at 400 °C in O2 atmosphere is performed to effectively reduce the acceptor-like trap states in the a-IGZO channel and the electric field in the etching-stop layer under the extended drain electrode, which participate in dynamic and DC degradation mechanisms, respectively. Thus, a-IGZO TFTs exhibiting excellent stability without any shift of the transfer curve under the same AC gate bias stress and AC drain bias stress are experimentally demonstrated simultaneously. [ABSTRACT FROM AUTHOR]

Dynamic degradation becomes a critical issue for thin-film transistors (TFTs) used in emerging new displays driven by high frequency gate voltage ${V}_{\text {G}}$ pulses. In this study, ${V}_{\text {G}}$ pulse rising edge dependent dynamic hot carrier degradation of poly-Si TFTs is investigated. It is demonstrated that rising edge of ${V}_{\text {G}}$ pulses which swing within the OFF-state of TFTs causes the degradation, while that of normal ${V}_{\text {G}}$ pulses which switch between the ON and OFF states across the flat band voltage ${V}_{\text {FB}}$ of TFTs does not. Based on transient TCAD simulation, the underlying mechanism of rising edge dependent degradation is proposed, which is based on the non-equilibrium PN junction degradation model previously proposed to explain ${V}_{\text {G}}$ pulse falling edge dependent degradation of poly-Si TFTs. Hence, the dynamic degradation model of poly-Si TFTs related to both rising and falling edge of the ${V}_{\text {G}}$ pulses can be unified now, which is applicable to fast gate pulses with steep rising and/or falling edges in sub- $\mu \text{s}$ level. [ABSTRACT FROM AUTHOR]

In this letter, the carrier mobility of amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) was remarkably enhanced by the introduction of nitrogen and the formation of Zn3N2, in which the saturation field-effect mobility ($\mu _{\text {sat}}$) was 61.6 cm2/Vs. Annealing temperature plays a key role on the enhancement of carrier mobility. When the annealing temperature was increased to 400 °C, $\mu _{\text {sat}}$ was reduced to 4.1 cm2/Vs, which was proposed to be due to the formation of defective ZnxNy based on X-ray photoelectron spectroscopy results. In addition, the a-IGZO TFT with enhanced mobility did not exhibit persistent photoconductivity behavior. The high carrier mobility could expand the application of a-IGZO TFTs to functional circuits in active-matrix displays. [ABSTRACT FROM AUTHOR]

The degradation mechanism of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under pulse drain bias stress is investigated. Although the degradation mechanism is found to be a dc one, the shift of the transfer curve under the pulse drain bias (0–20 V) is unexpectedly larger than that under dc drain bias (20 V) within the same equivalent stress time. The degradation mechanism is proposed to be tunneling and trapping of electrons in the etching stop layer during the pulse peak time and that in the gate dielectric during the pulse base time under the extended drain electrode region of the a-IGZO TFT, where the occurrence of the latter is triggered by the former. A solution for enhancing the stability of the a-IGZO TFT is also suggested. [ABSTRACT FROM AUTHOR]

Roles of gate voltage (VG) and stress power in self-heating (SH) degradation of amorphous InGaZnO thin-film transistors have been clarified. Normally observed positive threshold voltage (Vth) shift is attributed to the electron trapping mechanism, which is enhanced by both the effective VG and stress power. The effective VG plays a dominant role in most cases, while stress power takes control only if it is high enough. Following the positive Vth shift, a second-stage negative Vth backshift is also observed and is attributed to the water-related positive charges generation mechanism. It is enhanced by both stress power and effective VG for which stress power is found to be the dominant factor. [ABSTRACT FROM AUTHOR]

Degradations of elevated-metal metal oxide (EMMO) thin-film transistors (TFTs) under positive bias stress (PBS) and positive bias illumination stress (PBIS) are systematically investigated and compared. An intrinsic correlation between PBS and PBIS degradation is demonstrated. Continuous negative threshold voltage (Vth) shift is observed under both stresses, with similar time-dependent Vth shift and recovery behavior. Characterization parameters for dependencies of Vth shift on both stress VG and temperature are also very close for the two degradations. PBS and PBIS degradation of EMMO TFTs and their correlation can be consistently understood based on a unified model, which emphasizes stress-induced accumulation of doubly-ionized VO traps at the back-channel interface, and is verified with simulation. [ABSTRACT FROM AUTHOR]

Different from the conventional degradation phenomenon under positive bias stress (PBS), the shift of the transfer characteristic curve of polycrystalline silicon thin-film transistors (TFTs) to the negative gate bias direction after PBS is observed and reported. The PBS degradation is found to be recoverable and the recovery proceeds at a faster rate first and then continues at a much slower rate. The recovery can be further accelerated at a higher temperature or by applying a negative gate bias. After detailed data analysis, the degradation mechanism is proposed to be the generation of protons in the gate oxide and its accumulation at the channel/gate oxide interface. The proposed degradation model could explain both the degradation phenomena and the recovery behaviors of PBS degradation. [ABSTRACT FROM AUTHOR]

In this letter, investigations on the reliability of elevated-metal metal–oxide (EMMO) thin-film transistors (TFTs) under bipolar gate pulse stress are reported. Different from conventional amorphous indium–gallium–zinc oxide TFTs, EMMO TFTs exhibit negligible dynamic degradation during the pulse transitions and the device degradation is dominated by the DC mechanism. Though negative threshold voltage $({V}_{\textsf {th}})$ shift is observed under both positive bias stress (PBS) and negative bias stress, the ${V}_{\textsf {th}}$ shift caused by the bipolar pulse stress is smaller than that induced by the PBS with the same positive gate bias as in the bipolar gate pulse and the same effective PBS time, where the ${V}_{\textsf {th}}$ shift introduced during the positive bias stage in the bipolar pulse stress is believed to be partially recovered during the negative bias stage. These degradation phenomena are proposed to be due to the improved quality of the channel and the gate oxide with the oxidizing thermal heat-treatment during the fabrication of EMMO TFTs, which eventually lead to a reliable performance for the EMMO TFTs under bipolar gate pulse stress. [ABSTRACT FROM AUTHOR]

In this brief, a negative bias stress (NBS) induced degradation in n-type multigate polycrystalline silicon (poly-Si) thin-film transistor (TFT) is investigated. It is observed that after NBS the transfer characteristic curves shift to the negative gate bias direction and multigate TFTs degrade more than the single-gate TFTs with the same effective channel length. The observed degradation phenomenon is explained with short channel effect that is resulted from the diffusion and distribution of hole carriers in the channel, which are generated in the source/drain depletion region and swept into the channel when the junctions are reversely biased during NBS. Pronounced NBS degradation caused by increased hole carriers in the channel is also verified in NBS experiment with light illumination. [ABSTRACT FROM PUBLISHER]

In this paper, reduction of the gate-induced drain leakage (GIDL) current after drain bias sweeps for p-type polycrystalline-silicon thin-film transistor is reported, which is proposed to be due to local electron generation and trapping near the drain during the drain bias sweep in the kink current region. The reduction of the GIDL current during drain bias sweeps at successively lower gate biases undergoes a two-stage evolution behavior. The mechanism for the two-stage reduction behavior of the leakage current is clarified with the extraction and comparison of the activation energy for the leakage currents before and after the drain bias sweeps. Drain bias sweeps are also found effective in improving the uniformity of the leakage currents. [ABSTRACT FROM AUTHOR]

Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current ( \(I_\mathrm{{\scriptstyle ON}}\) ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hot-carrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation. [ABSTRACT FROM AUTHOR]

A physical-based analytical series resistance (Rs) model is first proposed to accurately evaluate the Rs of polycrystalline silicon thin-film transistors (TFTs). Through carefully analyzing the gate-to-source/drain overlap regions, three underlying physical effects wherein are adequately included, namely the gate (Vg)-induced carrier accumulation, current path spreading, and carrier transport via thermionic emission over grain boundaries. The proposed model can precisely reproduce the Vg dependent Rs behavior and fit the experimental data of both metal-induced lateral crystallized and excimer laser annealed TFTs. Furthermore, an explicit analytical expression of Rs is derived using appropriate approximation, based on which all underlying Rs components and their dependencies on device parameters can be clarified. Finally, feasible approaches of Rs reduction are suggested. [ABSTRACT FROM AUTHOR]