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The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section. [ABSTRACT FROM AUTHOR]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node. [ABSTRACT FROM PUBLISHER]

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints. [ABSTRACT FROM PUBLISHER]

With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits. [ABSTRACT FROM PUBLISHER]

Accurate estimation of single event upset rates for complex combinational logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS combinational logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30–60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify logic error rate calculations. [ABSTRACT FROM AUTHOR]

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits. [ABSTRACT FROM PUBLISHER]

Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of the flip/flops show only a 30%–50% difference between D- and DICE-Flip/Flop error rates and cross sections. Simulations are used to show that charge sharing is the primary cause for the similar failures-in-time (FIT) rates. Such small improvement in the single-event performance of the DICE implementation over standard D-Flip/Flop designs may warrant careful consideration for the use of DICE designs in 40 nm bulk technologies and beyond. [ABSTRACT FROM AUTHOR]

Charge-collection circuits were designed and fabricated in a 90 nm bulk CMOS process to examine the effects of charge sharing in sub-100 nm bulk CMOS processes. Laser interrogation of the charge-collection circuits provide the first direct verification of sub-100 am charge sharing effects and show the nodal spacing dependence of charge sharing. 3-D TCAD simulations corroborate the laser data and also show the use of guarddiodes as an effective charge sharing mitigation technique. [ABSTRACT FROM AUTHOR]

Single event latchup (SEL) in a 65 nm CMOS SRAM technology due to heavy ions is observed and device sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. Experimental results show the importance of testing at multiple lateral beam orientations to properly characterize device sensitivity. [ABSTRACT FROM AUTHOR]

The minimum laser energy required to cause sustained harmonic oscillations in a 201-stage ring oscillator varies little with increasing power supply voltage when operating in the subthreshold region. These small changes in threshold laser energy in the subthreshold region suggest that the cross-section curves as a function of power supply voltage remain relatively constant. Simulations show that the minimum pulsewidth required to generate higher-order oscillations decreases as operating voltage increases. Single-event transients are wider when circuits are operating in the subthreshold region than when operating at the nominal power supply voltages. Narrower single-event transients result for strikes on PMOS transistors as compared to those for strikes on NMOS devices in the subthreshold region; the opposite is observed when circuits are operating at the nominal power supply voltages. [ABSTRACT FROM PUBLISHER]

SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty. [ABSTRACT FROM PUBLISHER]

A built-in self-test technique for testing digital logic circuits for single-events has been developed. The BIST technique can be used for single-event testing in any conventional laboratory to evaluate the circuit level response to SEs. Experimental and simulation results for multiple technology nodes show the feasibility of this approach to test circuits, with the added advantages of reduced testing time and cost. [ABSTRACT FROM PUBLISHER]

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping. [ABSTRACT FROM AUTHOR]

Random Dopant Fluctuation (RDF) induced threshold voltage (Vt) variations affect two critical parameters used as a measure of Single Event (SE) Hardness (i) Single Event Transient (SET) pulse widths and (ii) Critical Charge (Qcrit). This causes an increase in the spread of SET pulse widths in sequential logic circuits and in the Qcrit required for Single Event Upsets (SEUs) in Static Random Access Memory Cells (SRAMs). Monte Carlo simulations show this can affect the hardness characterization in a commercial 90 nm process and a generic 65 nm technology. This necessitates statistical design approaches for validating conventional hardening schemes, to assure a required level of radiation tolerance in these deep submicron technologies. [ABSTRACT FROM AUTHOR]

In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of Charge deposited to cause an upset increases, and as the interconnect length increases. [ABSTRACT FROM AUTHOR]

A technique is proposed to selectively harden complex combinational logic circuits to single-event (SE) upsets. Propagation paths with sensitive nodes are identified and hardened while minimizing impact on circuit performance. [ABSTRACT FROM AUTHOR]

Cascode-voltage-switch logic family of gates is evaluated for single-event vulnerability. As the data is stored on two storage nodes for each logic gate in this logic family, as opposed to only one for static logic family, the single-event transient pulse does not propagate for more than a few stages. Simulation results show single-event transient pulse termination after one logic gate. Area, speed, and power requirements for cascode-voltage logic are comparable to that of static logic. [ABSTRACT FROM AUTHOR]