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The effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

The effects of radiation on memristors created using tantalum oxide and titanium oxide are compared. Both technologies show changes in resistance when exposed to 800 keV Ta ion irradiation at fluences above 1010 cm-2. TaOx memristors show a gradual reduction in resistance at high fluences whereas TiO2 memristors show gradual increases in resistance with inconsistent decreases. After irradiation TaOx devices remain fully functional and can even recover resistance with repeated switching. TiO2 devices are more variable and exhibit significant increases and decreases in resistance when switching after irradiation. Irradiation with 28 MeV Si ions causes both technologies to switch from the off-state to the on-state when ionizing doses on the order of 60 Mrad(Si) or greater (as calculated by SRIM) are reached without applying current or voltage to the part. Irradiation with 10 keV X-rays up to doses of 18 Mrad(Si) in a single step show little effect on either technology. TaOx and TiO2 memristors both show high tolerance for displacement damage and ionization damage and are promising candidates for future radiation-hardened non-volatile memory applications.

This document describes the radiation environments, physical mechanisms, and test philosophies that underpin radiation hardness assurance test methodologies. The natural space radiation environment is presented, including the contributions of both trapped and transient particles. The effects of shielding on radiation environments are briefly discussed. Laboratory radiation sources used to simulate radiation environments are covered, including how to choose appropriate sources to mimic environments of interest. The fundamental interactions of radiation with materials via direct and indirect ionization are summarized. Some general test considerations are covered, followed by in-depth discussions of physical mechanisms and issues for total dose and single-event effects testing. The purpose of this document is to describe why the test protocols we use are constructed the way they are. In other words, to answer the question: “Why do we test it that way”?

This document gives detailed test guidelines for single-event upset (SEU), single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) hardness assurance testing. It includes guidelines for both heavy-ion and proton environments. The guidelines are based on many years of testing at remote site facilities and our present understanding of the mechanisms for single-event effects.

A methodology for power MOSFET radiation hardness assurance is proposed. It is based on the statistical analysis of destructive events, such as gate oxide rupture. Examples of failure rate calculations are performed.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity.

Radiation effects are presented for the first time for vertically integrated 3 × 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.

The amounts of charge collection by single-photon absorption (SPA) and by two-photon absorption (TPA) laser testing techniques have been directly compared using specially made SOI diodes. For SPA measurements and some TPA measurements, the back substrates of the diodes were removed by etching with XeF2. With the back substrates removed, the amount of TPA induced charge collection can be correlated to the amount of SPA induced charge collection. There are significant differences, however, in the amount of TPA induced charge collection for diodes with and without substrates. For the SOI diodes of this study, this difference appears to arise from several contributions, including nonlinear-optical losses and distortions that occur as the pulse propagates through the substrate, as well as displacement currents that occur only when the back substrate is present. These results illustrate the complexity of interpreting TPA and SPA single-event upset measurements.

The effects of moisture on radiation-induced charge buildup in the oxides of a 0.35 μm SOI technology are explored. Data show no observable effects of moisture-related aging on radiation hardness. These results are in contrast to those of previous work performed on bulk MOS technologies fabricated in the 1980s. The cause of these differences do not appear to be due to differences in final chip passivation layers. Instead, other processing variables (including the use of different implant materials and thicker overlayers) may account for these differences. In any case, the SOI technology results indicate that not all advanced technologies exposed to moisture are necessarily susceptible to significant long-term radiation-induced aging effects.

Gate-all-around MOSFETs were fabricated from single-crystal silicon nanowires as small as 500 A? across. The response to x-rays was measured for transistors with various gate oxide thicknesses, a variety of physical designs, and several different electric fields during irradiation. While the devices are otherwise very well behaved, the total dose degradation is larger than expected and is attributable to thicker, non-uniform gate oxide grown on non-(100) Si surfaces of the nanowires.

It is shown that protons and neutrons can induce enhanced degradation in power MOSFETs, including both trench and planar geometry devices. Specifically, large shifts in current-voltage characteristics can be observed at extremely low proton total dose levels (as low as ~ 2 rad(SiO2)). These shifts can induce significant increases in device ldquooffrdquo state leakage current. Neutron irradiations show similar degradation at equivalent fluence levels, even though neutrons do not deposit dose due to direct ionization. These data suggest that the mechanism responsible for the enhanced degradation is a microdose effect associated with secondary particles produced through nuclear interactions between protons and neutrons and the materials in integrated circuits. The secondary particles deposit enough charge in the gate oxide to induce a parasitic drain to source leakage path in the transistor. Although the results are demonstrated here for only trench and planar geometry power MOSFETs, microdose effects can impact the radiation response of other integrated circuit types. Hardness assurances issues implications are discussed.

The propagation of single event transients (SET) is measured and modeled in SOI and bulk inverter chains. The propagation-induced pulse broadening (PIPB) effect is shown to determine the SET pulse width measured at the output of long chains of inverters after irradiation. Initially, narrow transients, less than 200 ps at the struck inverter, are progressively broadened into the nanosecond range. PIPB is induced by dynamic floating body effects (also called history effects) in SOI and bulk transistors, which depend on the bias state of the transistors before irradiation. Implications for SET hardness assurance, circuit modelling and hardening are discussed. Floating body and PIPB effects are usually not taken into account in circuit models, which can lead to large underestimation of SET sensitivity when using simulation techniques like fault injection in complex circuits.

For the first time, NROM-style nonvolatile memory elements were fabricated in SOI and irradiated. Total dose characterizations of these transistors indicate that this new style of memory can be functional to at least 500 krad (SiO2).

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H2O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H2. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H2 diffusion are considerably different than for H2O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a "propagation-induced pulse broadening" (PIPB) effect is observed. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification.

International audience; Abstract—We characterized the responses of three erbium-doped fibers with slightly different concentrations of rare-earth ions (240–290 ppm) and Al2O3 (7–10 wt.%) during proton and gamma-ray exposures. We have simultaneously measured the radiation-induced attenuation (RIA) around the Er3+ ion pumping wavelength (980 nm) and the associated changes of the Er3+ emission around 1530 nm. The three erbium-doped fibers show similar radiation responses. All fibers exhibit RIA levels between 9 10-3 and 1.7 10-2 dB m-1 Gy-1 at 980 nm and between 4 10-3 and 1.1 10-2 dB m-1 Gy-1 at 1530 nm. Protons and gamma-rays lead to similar radiation damages, with small differences between the protons of different energies (50 MeV and 105 MeV). Furthermore, we have performed online measurements of the spectral dependence of RIA from 600 to 1600 nm and offline measurements from 1200 to 2400 nm. The three fibers exhibit the same spectral response. Losses decrease monotonically from the visible to the infrared part of the spectrum. We have performed spectral decomposition of these RIA curves with the help of absorption bands previously associated with radiation-induced point defects. Our analysis shows that the main part of the RIA (600–1700 nm) in erbium-doped glass can be explained by the generation of Al-related point defects. The other defects related to the germanium and phosphorus doping of the silica seem to have a lower contribution to the induced losses. The Er3+ ion properties seem to be mainly unaffected by proton exposure, suggesting a solvation shell around the Er3+ ion formed by Al2O3 species.

Large, unexpected shifts in the current-voltage (IV) characteristics of commercial power MOSFETs irradiated with heavy ions have been observed. The shifts can be more than sixty-five times larger than the shifts resulting from total dose irradiation with gamma rays or electrons, and are shown to strongly depend on both the irradiation bias and the ion linear energy transfer (LET). These large shifts are a significant concern for devices intended to operate in low power space applications because it is shown that they can lead to off-state leakage currents greater than 1 A. The data are consistent with the formation of parasitic transistors resulting from the microdose deposited in the gate oxides of these devices by the heavy ions. These results have significant implications for hardness assurance testing of MOS devices for use in space.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(SiO2) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(SiO 2). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed

To explore the impact of temperature on the post-irradiation response of ICs, we characterized the temperature response of transistors, SRAMs, and a custom mixed-signal ASIC. Devices were irradiated at room temperature and electrically characterized post irradiation as a function of temperature. Devices exhibit significantly more parametric degradation when characterized at elevated temperatures. In addition to parametric degradation, it is demonstrated that post-irradiation elevated temperature characterization can also induce functional failures at significantly lower total dose levels than at room temperature. As a result, to ensure system functionality, it is essential that devices be characterized over the full system temperature range pre- and post-irradiation. Recommendations for incorporating temperature testing into a hardness assurance test method (i.e., Method 1019) are suggested. Methods for minimizing the detrimental effects of elevated temperature anneals on hardness assurance testing are also discussed

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO/sub 2/) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

著者人数：15名, 資料番号: SA1002017000

Microelectronic devices in satellites and spacecraft are exposed to high energy cosmic radiation. Furthermore, Earth-based electronics can be affected by terrestrial radiation. The radiation causes a variety of Single Event Effects (SEE) that can lead to failure of the devices. High energy heavy ion beams are being used to simulate both the cosmic and terrestrial radiation to study radiation effects and to ensure the reliability of electronic devices. Broad beam experiments can provide a measure of the radiation hardness of a device (SEE cross section) but they are unable to pinpoint the failing components in the circuit. A nuclear microbeam is an ideal tool to map SEE on a microscopic scale and find the circuit elements (transistors, capacitors, etc.) that are responsible for the failure of the device. In this paper a review of the latest radiation effects microscopy (REM) work at Sandia will be given. Different SEE mechanisms (Single Event Upset, Single Event Transient, etc.) and the methods to study them (Ion Beam Induced Charge (IBIC), Single Event Upset mapping, etc.) will be discussed. Several examples of using REM to study the basic effects of radiation in electronic devices and failure analysis of integrated circuits will be given.

This work investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies.

We examine the radiation response, annealing characteristics, and long-term reliability of capacitors with Al gates and Al/sub 2/O/sub 3/-SiO/sub x/N/sub y/ gate dielectrics stacks which received a forming gas anneal (FGA) or an O/sub 2/ and FG anneal after high-/spl kappa/ deposition. By comparison to a theoretical capacitance-voltage (CV) curve, the FG annealed devices are found to have a large preirradiation interface trapped charge density of /spl sim/7/spl times/10/sup 11/ cm/sup -2/, whereas devices annealed in O/sub 2/ and FG show a large density (/spl sim/9/spl times/10/sup 11/ cm/sup -2/) of negative bulk charge. The midgap voltage shift (/spl Delta/V/sub mg/) increases monotonically with dose for both sets of devices, but the O/sub 2/ annealed devices exhibit 50% less trapping at a total dose of 2 Mrad(SiO/sub 2/). The radiation-induced voltage shifts are found to recover during long duration biased anneals as a result of tunneling and thermal annealing. For short times and large biases, the annealing response is found to be dominated by tunneling. After 1,000 s of annealing, there is a 50% reduction in /spl Delta/V/sub mg/ for devices annealed at 2.0 MV/cm and a 7.5% recovery for devices annealed at 1.0 MV/cm. For longer times, the annealing response of these devices is dominated by thermal annealing. Accelerated life testing shows these devices have a broad failure distribution with a large population of extrinsic failures. Extrapolation of the reliability data suggests these particular devices would have to be operated at an electric field less than /spl sim/2.5 MV/cm to achieve a ten-year operational lifetime. Improved reliability is, therefore, required before insertion into a manufacturing environment.

Mechanisms for single-event gate rupture (SEGR) in MOS capacitors and linear integrated circuits (ICs ) are explored at ion energies greater than 1 GeV. We find that SEGR thresholds depend strongly on ion energy, but are independent of oxide defects, bias polarity, doping concentration, and ionizing dose. The number of SEGR strikes across a MOS capacitor was measured, and the SEGR response cross section distinctly shows an electric field threshold. The importance of having stiffening and speedup capacitors at the device is discussed.

The high and low dose rate responses of bipolar transistors in a bipolar linear circuit process technology have been studied with specially designed gated lateral pnp test transistors that allow for the extraction of the oxide trapped charge (N/sub ot/) and interface trap (N/sub it/) densities. The buildup of N/sub ot/ and N/sub it/ with total dose is investigated as a function of the irradiation gate voltage at 39 rad/s and 20 mrad/s for three variations of the final passivation layer (all variations had the same oxide covering the active region of the devices). The three variations in final passivation were selected to exhibit minimal degradation at high and low dose rate (no passivation), significant degradation at high and low dose rate (p-glass/nitride) and enhanced low dose rate sensitivity (ELDRS) (p-glass only). It is shown that the increase in base current is dominated by increased N/sub it/ and the "true" low dose rate enhancement in the ELDRS parts occurs for zero and negative gate voltage, but is eliminated for large positive gate voltage and elevated temperature irradiation. Implications for ELDRS models are discussed.

The development of simple and rapid methods for the detection of the common genetic mutations associated with cystic fibrosis (CF) requires access to positive-control samples including the 5/7/9T variants of intron 8. We used PCR and a simple multiplex bead-array assay to identify 5/7/9T control samples from 29 commercially available DNA samples. Unpurified PCR products were directly hybridized to color-coded beads containing allele-specific capture probes for 5/7/9T detection. The performance of the assay was investigated using reverse-complement oligonucleotides, individual PCR products, and multiplex PCR products for 5/7/9T detection within a complex CFTR screening assay. Samples were genotyped by grouping the relative signal intensities from each capture probe. Of 29 commercially available DNA samples analyzed, 2 5T/7T, 2 5T/9T, 9 7T/9T, 11 7T/7T, and 5 9T/9T genotypes were identified. The genotype within each sample group was confirmed by DNA sequencing. The assay was compatible with the analysis of 10 to 1000 ng of genomic DNA isolated from whole blood and allowed for the separate identification of primary CFTR mutations from reflex variants. The correct identification of positive controls demonstrated the utility of a simple bead-array assay and provided accessible samples for assay optimization and for routine quality control in the clinical laboratory.

Implanting the buried oxide of silicon-on-insulator technologies can create electron traps throughout the buried oxide that can compensate the buildup of radiation-induced positive charge. These can be used as an effective method for total-dose hardening buried oxides in SOI devices. In this work, we show that implanting buried oxides can also create thermally activated metastable electron traps near the top Si/SiO2 border. These metastable electron traps can produce significant bias instabilities in the back-gate transistor characteristics and lead to threshold voltage instabilities in fully-depleted devices.

Silicon-on-insulator (SOI) technologies, have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially-depleted transistors and decrease the threshold voltage and increase the leakage current of fully-depleted transistors. We review process and design techniques that have been developed to reduce the net amount of radiation-induced positive charge trapped in the buried oxide or to mitigate the effects of trapped charge in the buried oxide, respectively. We also compare the total dose response of devices operated in single-gate (SO) and double-gate (DG) mode as a function of silicon film thickness. DG-MOSFETs are systematically less sensitive to radiation-induced trapped charge and interface trap.

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of present day and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM.

An increased single event upset cross-section was found in some silicon-on-insulator (SOI) devices in recent experiments. In order to investigate this unexpected increase we performed both broad beam and microbeam experiments on thermal oxide capacitors. Charge collection was measured using ion beam induced charge collection (IBICC) and time resolved IBICC under different biasing conditions. Lateral charge collection profiles were recorded across the top electrode. We found that the collected charge strongly depends on the applied bias and the oxide thickness. Lateral non-uniformity was observed for low bias conditions. In this paper we will give a qualitative explanation for the charge collection mechanism in SOI devices.

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits.

High-energy ion-irradiated 3.3-nm oxynitride film and 2.2-nm SiO/sub 2/-film MOS capacitors show premature breakdown during subsequent electrical stress. This degradation in breakdown increases with increasing ion linear energy transfer (LET), increasing ion fluence, and decreasing oxide thickness. The reliability degradation due to high-energy ion-induced latent defects is explained by a simple percolation model of conduction through SiO/sub 2/ layers with irradiation and/or electrical stress-induced defects. Monitoring the gate-leakage current reveals the presence of latent defects in the dielectric films. These results may be significant to future single-event effects and single-event gate rupture tests for MOS devices and ICs with ultrathin gate oxides.

TaO x and TiO 2 memristors have been irradiated with 800 keV Ta ions, 28 MeV Si ions, and 10 keV X-rays. TaO x devices were also irradiated with 70 keV electrons. Displacement damage effects are studied using 800 keV Ta ions and both technologies show changes in resistance for fluences greater than 1010 cm−2. TaO x devices show gradual resistance degradation in the off-state with increasing fluence. TiO 2 devices show gradual inconsistent increases in off-state resistance with inconsistent abrupt decreases. TaO x devices show more stability and consistent off-state resistances than TiO 2 devices. Ionization effects are investigated using 28 MeV Si ions, 70 keV electrons, and 10 keV X-rays. During 28 MeV Si irradiation, both technologies change from the off-state to the on-state when a critical ionizing dose is reached without applying voltage or current to the device. The critical threshold is calculated using SRIM to be on the order of 60 Mrad(Si) or higher. 10 keV X-ray irradiation of doses up to 18 Mrad(Si) per step show little effect on either technology. A single TaO x device irradiated with 70 keV electrons changed from the offstate to the on-state at a calculated dose on the order of 100 krad(Si), suggesting a difference in charge yield compared to the 28 MeV Si irradiation.

The effects of substrate and epitaxial-layer thickness on the single-event upset and single-event latchup response of integrated circuits are studied using experiments and three-dimensional device simulations. Reducing substrate thickness can be an effective method for improving single-event upset and latchup immunity, but only if devices are thinned beyond their epitaxial-layer thickness. Increases in overall single-event upset threshold linear energy transfer of more than a factor of two are predicted after thinning to a wafer thickness of 0.5 /spl mu/m. Simulations predict that the single-event latchup performance of a thinned integrated circuit will be similar to that of the same integrated circuit fabricated on an epitaxial substrate of equivalent thickness. By combining wafer thinning with backside contact formation, more significant improvements in the single-event latchup threshold can be obtained.

Submicron nonvolatile memory transistors were fabricated by exposing silicon-on-insulator (SOI) buried oxides to hydrogen at elevated temperatures to generate mobile protons in the buried oxides. By switching the polarity of the bias to the SOI substrate, the mobile protons in the buried oxide were transported to either the top or bottom Si–buried oxide interface, switching the leakage current of top gate transistors from an ON to an OFF state.

Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an interesting saturation effect of SES versus the amount of injected charge is observed.

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.

LM111 voltage comparators exhibit a wide range of total-dose-induced degradation. Simulations show this variability may be a natural consequence of the low base doping of the substrate PNP (SPNP) input transistors. Low base doping increases the SPNPs collector to base breakdown voltage, current gain, and sensitivity to small fluctuations in the radiation-induced oxide defect densities. The build-up of oxide trapped charge (N/sub OT/) and interface traps (N/sub IT/) is shown to be a function of pre-irradiation bakes. Experimental data indicate that, despite its structural similarities to the LM111, irradiated input transistors of the LM124 operational amplifier do not exhibit the same sensitivity to variations in pre-irradiation thermal cycles. Further disparities in LM111 and LM124 responses may result from a difference in the oxide defect build-up in the two part types. Variations in processing, packaging, and circuit effects are suggested as potential explanations.

In this work we explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10 keV X-rays. Our results show that increases in radiation-induced leakage current are caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current may be amplified to considerably higher levels by impact ionization. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. Large increases in leakage currents can be obtained with or without impact ionization occurring in the channel region. For these transistors, the worst-case bias configuration was determined to be the "ON" bias configuration for both the cases where radiation-induced transistor response was dominated by charge buildup in the buried oxide and in the trench sidewall isolation. These results have important implications on hardness assurance.

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are 1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or 2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. We call this structure the BUSFET-Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source.

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 /spl mu/m and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 /spl mu/m. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

Effects of irradiation and annealing temperature on radiation-induced charge trapping are explored for MOS transistors. Transistors were irradiated with 10-keV x rays at temperatures from -25 to 100/spl deg/C and annealed at 100/spl deg/C for times up to 3.6/spl times/10/sup 6/ s. Transistor data were analyzed for the contributions of radiation-induced charge due to oxide traps, border traps, and interface traps. Increased irradiation temperature resulted in increased interface-trap and border-trap buildup and decreased oxide-trapped charge buildup during irradiation. Interface-trap buildup immediately following irradiation for transistors irradiated at 100/spl deg/C was equivalent to the buildup of interface traps in transistors irradiated at 27/spl deg/C and annealed for one week at 100/spl deg/C (standard rebound test). For the p-channel transistors, a one-to-one correlation was observed between the increase in interface-trap charge and the decrease in oxide-trapped charge during irradiation. This may imply a link between increased interface-trap buildup and the annealing of oxide-trapped charge in these devices. The observed data can be explained in terms of increased hydrogen ion transport rates to the Si/SiO/sub 2/ interface during elevated temperature irradiations. These results have implications on hardness assurance testing and potentially may be used to reduce costs associated with rebound qualification.