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This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 GΩ and 700 GΩ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

This brief analyzes the operation of the three-inverter Schmitt trigger (TI-ST) at ultra-low supply voltages. Included in the analysis is a model to predict the supply voltage at which the TI-ST changes from the amplifier mode to the hysteresis mode. We show theoretically that the TI-ST can exhibit hysteresis for a supply voltage as low as the fundamental limit of unity gain of the CMOS inverter. We also demonstrate experimentally that, with a suitable design, hysteresis starts to occur from a supply voltage as low as 48.5 mV. A relaxation oscillator built with a TI-ST and standard inverters is experimentally demonstrated to start to oscillate from supply voltages as low as 62 mV.

The use of digital schemes to indirectly detect the zero-current crossing and perform the zero-current switching in ultra-low-voltage inductive boost converters has been prevalent in recent developments. However, design guidelines for such digital schemes are still lacking. In this brief, an efficient zero-current switching scheme for ultra-low-voltage boost converters is proposed and implemented in standard CMOS 130 nm technology. Instrumental to our design was the introduction of the proper time delay for sensing the direction of the inductor current on the opening of the high-side switch. The correct delay time as a function of the circuit parameters keeps the switching as close as possible to the zero-current crossing. Owing to an efficient zero-current-switching scheme, the fabricated prototype provides end-to-end efficiency of 76% for a voltage converter having an input voltage as low as 20 mV.

A DC-DC boost converter for ultra-low-voltage thermal energy harvesting is presented herein. The focus of this brief is to provide both self-startup and efficient conversion at ultra-low input voltages. The converter startup is achieved through the use of a cold starter based on an ultra-low-voltage oscillator and a charge pump. The inductive boost converter architecture uses two low-side switches in order to independently optimize the low-voltage startup and the steady-state conversion efficiency. The model of the developed converter allows optimization of the boost switches as a function of the TEG internal resistance and input voltage. A zero current switching circuit with accurate detection for low input voltages is designed and implemented. The prototype fabricated in 130 nm standard CMOS technology achieves startup for an input voltage of 11 mV and, once started, the system can perform the boost operation for input voltages as low as 7.3 mV, delivering 50% of end-to-end efficiency at 10.5 mV and peak end-to-end efficiency of 85% at 140 mV.

This brief describes a compact test chip in a 130-nm CMOS technology, aimed at characterizing both the short- and long-channel transistors and the series association of halo-implanted transistors. The chip contains a set of low-threshold-voltage (LVT) nMOS/pMOS transistors with several channel lengths and transistors associated in series. Parameters, such as threshold voltage, specific current, and intrinsic voltage gain, were determined through simulation and measurements of 20 chips. The results reported herein provide integrated circuit designers with guidelines for choosing either long-channel lengths or series association of transistors to comply with the requirements of their design.

In this brief, we analyze the operation of the classical Schmitt trigger (ST) circuit as an ultra-low-voltage (ULV) amplifier. Small-signal analysis is employed in order to determine optimum relative transistor sizes, which maximize the voltage gain. A comparison of the classical ST with the standard inverter highlights the relative benefits and drawbacks of each for operation as an amplifier in ULV applications. It is shown that the theoretical minimum supply voltage of the ST for voltage amplification (absolute voltage gain ≥ 1) is 31.5 mV at 300 K, which is below the well-known 36 mV limit of the standard inverter. Two test chips in a 180 nm technology with ST circuits built from transistors with different relative sizes were fabricated. For ${\boldsymbol {V}}_{\mathrm{ DD}} = 60$ mV and 100 mV, the values measured for the voltage gain of the ST were 6 and 32 dB, respectively, which are significantly higher than the values of 4.4 and 15 dB simulated for the standard inverter at the same supply voltages.

This paper presents the design and testing of a self-biased current source. The design described in this paper is based on the concept of inversion coefficient, which allows a direct calculation of the dispersion in the output current in terms of the internal bias errors and transistor mismatch. The circuit was fabricated in a standard CMOS 180 nm technology.

The ISFET (Ion Sensitive Field Effect Transistor) is a structure based on the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is capable of measuring ionic concentration of a solution. The ISFET has been used for such areas as DNA sequencing, viruses and bacteria detection. The basic idea behind the ISFETs emerged in 1970, but a deeper understanding of some of its non-idealities and the development of architectures to reduce their effects are still needed. For that reason, this work revisits the basic principles of ISFET operation. The ISFET modeling using the binding site theory, Gouy-Chapman-Stern model and the Advanced Compact Model of the transistor is introduced and implemented in Matlab®. Furthermore, the details of a chip designed on the Virtuoso® platform, aimed at characterizing the ISFETs on the SilTerra D18V technology, are presented. Simulation results estimate an average sensitivity of 45.3 mV/pH for the designed devices over a pH range from 1 to 10. The chip sent for fabrication was kindly supported by Chipus Microeletronica S.A. and SilTerra Malaysia Sdn Bhd.

A compact presentation of the basic theory of the MOS transistor is given. Instead of the usual approach of furnishing separate analytical formulas for the strong and weak inversion regions of the MOS transistor, we provide simple formulas which are valid in all operating regions, including moderate inversion. We review ultra-low-power circuits operating near the threshold condition that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are the most fundamental parameters for technology characterization, circuit design, and testing.

This work proposes a new architecture of a CMOS analog multiplier based on transistors operating in nonsaturation region, from weak to strong inversion, featuring low sensitivity to voltage supply variations. In addition, the multiplier shows desirable characteristics for the compact implementation of Cellular Neural Networks, namely both voltage and current inputs, current output, and modularity. Simulation results have demonstrated low power consumption and low sensitivity to supply voltage.

This paper presents two fully integrated inductive ring oscillators that operate with supply voltages below 2kT/q for energy harvesting applications. Expressions for the oscillation frequency as well as the minimum transistor gain and supply voltage required for the starting up of oscillations are derived for each topology. The experimental results for two cross-coupled oscillators, with topologies comprised of a single-inductor and two-inductors per stage, are presented. The two oscillators operate with supply voltages as low as V DD = 46 mV at 11.5 µW DC power and V DD = 31 mV at 15 µW DC power, respectively, thus confirming the extremely low voltage operation of the prototypes integrated in a 130 nm technology.

In order to investigate the minimum supply voltage for MOSFET oscillators, three topologies were studied. Two of them, namely the enhanced swing inductive-load ring and the enhanced swing Colpitts oscillators, can operate with supply voltages below the thermal voltage. Simplified theoretical expressions for the minimum supply voltage of the oscillators were derived. Measurement results obtained using prototypes built with zero-VT transistors and high-quality-factor inductors confirmed the operation of one of the oscillators down to a supply voltage below 5 mV.

This letter presents MOS analog circuits that can operate with very low supply voltages. Operation of the MOS transistor in the triode region is emphasized owing to the limited voltages available. Special attention has been given to the properties of the zero-VT transistor due to its high drive capability at low voltages. Simulation and measurement results for a Colpitts oscillator prototype set up around a zero-VT MOSFET demonstrated that the oscillator operates with supply voltages lower than the thermal voltage kT/q. Finally, ultra-low-voltage rectifiers using diodes or diode-connected MOSFETs operating in weak inversion are analyzed.

The authors propose a four-quadrant multiplier based on a core cell that exploits the general relationship between the saturation current of an MOS transistor and the source inversion charge density, valid from weak to strong inversion. The advantages of the proposed circuit are simplicity, low distortion and feasibility of low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1 for an input current of 80 of the full-scale range. The multiplier core area is around 10 000 m 2 .

A relaxation oscillator is presented that makes use of a current-mode Schmitt trigger to reduce the effects of process, voltage and temperature (PVT) variations. A detailed analysis of the oscillator, including the temperature performance, is presented and verified by experimental results. A test chip with a typical frequency of 32 kHz was fabricated in a 0.18 μm standard CMOS process. The measured frequency variations were +/− 30 ppm/°C for temperature variation from −20 °C to 80°C and +/− 500 ppm/V for supply voltage variation from 0.7 V to 1.8 V. The short term stability is 66 ppm (2 ns) of jitter while the long term stability is 500 ppm of Allan deviation after 10 seconds. A careful design results in a total area of 0.1 mm2 and a power consumption of 150 nW.

This work presents a self-biased MOSFET threshold voltage V T0 monitor. The threshold condition is defined based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit consists in balancing two self-cascode cells operating at different inversion levels, where one of the transistors that compose these cells is biased at the threshold condition. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. We propose a process independent design methodology, evaluating different trade-offs of accuracy, area and power consumption. Schematic simulation results, including Monte Carlo variability analysis, support the V T0 monitoring behavior of the circuit with good accuracy on a 180 nm process.

Digital and analog ICs generally rely on the concept of matched behavior between identically designed devices. Time-independent variations between identically designed transistors, called mismatch, affect the performance of most analog and even digital MOS circuits. This article focuses on the analysis of mismatch in MOS transistors resulting from random fluctuations of the dopant concentration, first studied by Keyes. Today, we recognize these fluctuations as the main cause of mismatch in bulk CMOS transistors.

The migration of an analog circuit to a new technology usually requires a complete redesign. With the procedure presented, designers can calculate parameters for a given circuit in a new technology, starting from the same design in an earlier technology. The procedure's simple resizing rules have been verified with standard MOSFET simulation models.

This paper presents an ultra-low-voltage step-up converter for energy harvesting applications, which is able to operate from supply voltages below the thermal voltage kT/q. The operation of the main blocks of the converter, namely an enhanced swing ring oscillator and a Dickson charge pump, both operating at ultra-low voltage, is described. The extremely low voltage operation, made feasible through the arrangement presented, is demonstrated via a prototype built with off-the-shelf devices and zero-VT transistors in a 130 nm CMOS technology. The prototype generates a DC output equal to 1V at current consumptions of 10 nA and 1 µA from input voltages of 10 and 25 mV, respectively.

Texto completo: acesso restrito. p.481–485 Submitted by Suelen Reis (suelen_suzane@hotmail.com) on 2013-01-18T13:46:26Z No. of bitstreams: 1 Cunha.pdf: 180004 bytes, checksum: 708710ed1fdce16a5cd2e9d7ac746238 (MD5) Made available in DSpace on 2013-01-18T13:46:26Z (GMT). No. of bitstreams: 1 Cunha.pdf: 180004 bytes, checksum: 708710ed1fdce16a5cd2e9d7ac746238 (MD5) Previous issue date: 1999 This paper presents a physical derivation of the unified charge control model (UCCM) [Park C-K, Lee C-Y, Lee K, Moon B-J, Byun YH, Shur M. IEEE Trans Electron Dev 1991;ED-38:399; Lee K, Shur M, Fjeldly TA, Ytterdal T. Semiconductor device modeling for VLSI. Englewoods Cliffs: Prentice Hall, 1993.], which describes the relationship between inversion charge density and the applied voltages in the MOS transistor for any operating region. Using the UCCM and the MOSFET charge model presented in Cunha et al. [Cunha AIA, Schneider MC, Galup-Montoro C. Solid-St Electron 1995;38:1945.], we develop a MOSFET model formulated in terms of the drain current in saturation. Based on this model, a methodology for the extraction of the UCCM parameters is proposed.

Texto completo: acesso restrito. p.1510-1519 Submitted by Suelen Reis (suelen_suzane@hotmail.com) on 2013-01-25T12:13:00Z No. of bitstreams: 1 Cunha.pdf: 289468 bytes, checksum: d553ef47764ff7358568970f4f62f210 (MD5) Made available in DSpace on 2013-01-25T12:13:00Z (GMT). No. of bitstreams: 1 Cunha.pdf: 289468 bytes, checksum: d553ef47764ff7358568970f4f62f210 (MD5) Previous issue date: 1998-10 This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

This paper presents a fully integrated enhanced swing Colpitts oscillator that operates from supply voltages below 4kT/q. Design equations considering the oscillation frequency and start-up conditions required for operation of the Colpitts oscillator are derived. The oscillator was built with a zero-VT transistor, due to its high drive capability at low voltages. Measurement results obtained for a prototype integrated in the IBM 130 nm technology demonstrated the operation of the oscillator with 86 mV of supply voltage.

Texto completo. Acesso restrito. p. 1945-1952 Submitted by Santiago Fabio (fabio.ssantiago@hotmail.com) on 2013-09-11T20:28:43Z No. of bitstreams: 1 5555555555555555555.pdf: 686241 bytes, checksum: 8bfea2e2113858d64ba02ec950907cae (MD5) Approved for entry into archive by Rodrigo Meirelles (rodrigomei@ufba.br) on 2013-11-16T11:57:27Z (GMT) No. of bitstreams: 1 5555555555555555555.pdf: 686241 bytes, checksum: 8bfea2e2113858d64ba02ec950907cae (MD5) Made available in DSpace on 2013-11-16T11:57:28Z (GMT). No. of bitstreams: 1 5555555555555555555.pdf: 686241 bytes, checksum: 8bfea2e2113858d64ba02ec950907cae (MD5) Previous issue date: 1995 This paper presents a long-channel MOSFET model wherein the drain current, total charges and small-signal parameters for quasi-static operation are very simple functions of the inversion charge densities at the channel boundaries. The inversion charge densities, in turn, are formulated as explicit continuous functions of the terminal voltages, with continuous first order derivatives, resulting in an explicit MOSFET model valid in the whole inversion region. Physical properties, such as the symmetry of the transistor with respect to source and drain are carefully observed in order to achieve a proper prediction of the device behavior. The proposed model contains only the classical parameters of the MOSFET theory. Salvador

This work discusses two fundamental blocks of an in vivo MOS dosimeter, namely the radiation sensor and the V T -extractor circuit. It is shown that threshold extractor circuits based on an all-region MOSFET model are very appropriate for low power design. The accuracy of the extractor circuits allows using the PMOS transistors of the integrated circuit CD4007 as the radiation sensor in a dosimeter for radiotherapy applications.

This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >

This chapter begins with a rapid overview of CMOS technology for circuit designers, including the description of a simplified deep-submicron CMOS structure and its process flow as well as the main parameters of some representative processes. The devices available in CMOS processes, including resistors, capacitors, inductors, and bipolar transistors, are then reviewed. The main electrical parameters of the passive devices are presented. Some design issues related to the use of sub-wavelength optical lithography are addressed in the introduction to the layout sections. Finally, layout topics, including design rules and layout for manufacturability, for matching, and for transistor associations, are presented. An overview of CMOS technology MOS integrated circuits (ICs) have been manufactured for volume delivery ever since 1970. Taking advantage of the scalability of the MOS transistors, micron technologies were developed during the 1980s and deep-submicron technologies appeared in the 1990s. In this chapter we will briefly review some deep-submicron processes that are currently (2009) employed for analog design. Basic process steps in monolithic IC fabrication Monolithic ICs are fabricated on high-quality monocrystalline silicon substrates called wafers, with diameters as large as 300 mm and thicknesses up to 1250 μm. The fabrication process enables the achievement of appropriate geometries in the semiconductor and in the insulating and conducting layers deposited on the semiconductor substrate. The fabrication process consists of a series of elementary steps that allows the patterning of the semiconductor substrate and the modification of its electrical properties by selective doping as well as the deposition, removal, and patterning of conducting and insulating layers.

Analog filters, essential parts in many different electronic systems, can be implemented in CMOS using switched-capacitor (SC), switched-current (SI), active- RC , MOSFET-C, or OTA-C techniques. Owing to their considerable importance in analog CMOS circuits, Chapter 10 will focus on SC circuits. In this chapter, we study the MOSFET-C and OTA-C techniques, which have been the most important ones for the realization of continuous-time (CT) integrated filters in CMOS technologies. Applications of CT filters include anti-aliasing and reconstruction filters, read channels of disk drives, data-communication circuits, and high-speed data links. A disadvantage of CT filters is that the filter coefficients are sensitive to process and temperature variations and aging. Therefore, tuning of the components that determine the frequency response is required. In this chapter, we will concentrate on the fundamental aspects of filter design at the component level and on the basic building blocks for each technique. We will describe some of the main limitations of the MOSFET-C and OTA-C techniques and the concepts of some tuning schemes used for keeping the filter transfer function close to the nominal specifications. The synthesis of high-order filters, which can be found in more specialized texts such as, is not the subject of this chapter. Basics of MOSFET-C filters The MOSFET-C (MOSFET-capacitor) is a mature technique for the integration of CT filters in CMOS technologies. MOSFET-C circuits are similar to the active- RC topologies composed of operational amplifiers, resistors, and capacitors.

The first part of this chapter is dedicated to the MOS sample-and-hold circuit (S/H). The main physical limitations of the MOS S/H, namely switch on-resistance, thermal noise, and switch charge injection, are reviewed. Distortion produced by the non-linear switch resistance is modeled and some circuit-linearization techniques for MOS switches are introduced as well as low-voltage circuit techniques. Finally, clock-jitter effects on the MOS S/H are modeled and these effects in analog-to-digital converters are commented on. The second part of the chapter presents the basics of switched-capacitor (SC) circuits. Parasitic insensitive integrators and second-order filters are reviewed. Amplifier specifications for SC circuits are detailed, as well as some circuit techniques to reduce the effects of op-amp imperfections. The important topic of SC circuits fully compatible with digital MOS technology ends the section on SC circuits. The last part of the chapter briefly introduces alternative switched circuits, specifically switched-MOSFET and switched-current filters. MOS sample-and-hold circuits Sample-and-hold (or track-and-hold) circuits are ubiquitous in signal-processing circuits. They are used at the front end of analog-to-digital (A/D) converters and at the back end of digital-to-analog (D/A) converters. The signal-to-noise ratio of an A/D converter is usually limited by the performance of the sample-and-hold block. Furthermore, precision analog integrated circuits are mostly implemented by sampled-data circuits in which the basic building block is the S/H. Sample-and-hold basics An ideal S/H is depicted in Figure 10.1. During the sampling mode, the switch S is on and the output voltage tracks the input voltage.

The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD >

In this paper we propose a four-quadrant multiplier based on a core cell that exploits the relationship between the saturation current of an MOS transistor and the source transconductance. The advantages of the proposed topology are simplicity and feasibility of low-power and low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1% for an input current equal to 80% of the full scale range. The multiplier area is around 10,000 mum2.

This paper presents a new approach for accurate M-2M MOSFET digital-to-analog converter (DAC) design. It describes a complete design methodology, where DAC inaccuracy is related to transistor geometry and bias through a powerful physics-based MOSFET mismatch model, very useful for hand design. Short-channel effects are also taken into account. Two versions of the converter were implemented in a 0.35 mum 3.3 V CMOS technology, and corroborate the theoretical development with statistical experimental results.

This paper presents the temperature performance of two self-biased current sources. We have employed a simple topology to design 4 nA and 900 pA current references implemented in both 0.35 mum and 0.18 mum technologies, respectively. Experimental results showed that the current source implemented in 0.35 mum technology can operate at a supply voltage as low as IV and at 650 mV in 0.18 mum CMOS technology. The temperature performance of the current source is analyzed in this paper. The association of a very simple topology, an efficient design procedure, low voltage cascode transistor and low output conductance trapezoidal transistors has resulted in small area, ultra low power consumption and a line regulation better than 0.2%/V of supply voltage.

This paper presents a simple model of the Early voltage for the MOS transistor operating in weak and moderate inversion. The model is based on a decomposition of the transistor channel into a region where the gradual-channel approximation holds and a region that is modeled as a reverse- biased junction. Measurements of the characteristics of both n- and p-channel transistors with different channel lengths in a 0.35 mum technology demonstrate the feasibility of the proposed model.

In this paper, a new technique called 'switched inverter' for analog sample data signal processing is proposed. The circuit is based on the conventional CMOS inverter operating as a transconductor. The proposed circuit does not require linear capacitors and employs switches that operate at fixed channel voltage. Owing to the use of inverters, the proposed structure presents class-AB operation. A 8'th taps FIR filter has been designed in a standard 0.35-μm CMOS technology at 0.6 V supply.

This paper describes a test circuit for intensive characterization of MOS transistors mismatch. It aggregates analog switches, a shift register and a reference circuit, as well as the matrix of 1296 transistors to be tested. This circuit was integrated in a 0.35 mm bulk technology, and was designed to give experimental support for our MOSFET mismatch model. The test chip was characterized over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, allowing the analysis of MOSFET mismatch from bias, process and geometric parameters.

This paper presents a reuse procedure of analog circuits which is based on a scalable model of the MOSFET. A set of very simple expressions allows the calculation of the transistor dimensions and bias of a given circuit in a new generation technology, based on a previous design of the same circuit in an earlier technology.

Adequate and understandable MOSFET models are presently a must for the design of integrated circuits. Most of the existing MOSFET models, however, are too complex and/or do not comply with basic principles of physics. We propose here the use of ACM model, a very simple transistor model, together with a set of easily implemented experiments to determine the ACM parameters for the training of students for integrated circuit design. The use of the ACM model by our students has allowed them to easily correlate the model parameters and the electrical characteristics of MOSFETs.

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.

This paper presents MOSVIEW, a graphical tool for transistor-level design of analog MOS circuits. MOSVIEW allows students to visualize and explore the design space in order to size and bias the transistor for a given set of specifications.

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters.

This paper presents the design of an ultra-low-power self-biased 400 pA current source. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ (0.027 mm/sup 2/) in the AMIS 1.5 /spl mu/m (TSMC 0.35 /spl mu/m) CMOS technology and power consumption around 2 nW for 1.2 V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1 V with a good regulation (

This paper presents a CMOS low-voltage operational amplifier (opamp), which uses a minimum selector circuit to control the class AB operation of the output stage. The opamp basic characteristics are analyzed and simulated using the SMASH 4.0 simulator with the ACM model of the MOSFET. The supply voltage is 1.5 V and the total quiescent current is 4 /spl mu/A for a unity-gain frequency of 1 MHz. The class AB opamp was designed to operate in a sample-hold of the switched-MOSFET technique (SM), supplying a load with RC characteristic.

This paper presents a new compact model for the intrinsic charges and (trans) capacitances of the MOSFET including short-channel effects such as drain induced barrier lowering (DIBL), channel length modulation (CLM) and carrier velocity saturation. Explicit and compact expressions for charges and (trans) capacitances valid in all regimes of operation are presented. Simulations examples that illustrate short-channel effects in charges and (trans) capacitances are shown.

This paper presents a design procedure for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. It is shown that in most cases there is an optimum bias in moderate inversion for which the attainable DC gain is maximum. The design and measurements on a common-source amplifier illustrate the appropriateness of the proposed methodology.

Results concerning the implementation of switched capacitor (SC) filters with weakly nonlinear capacitors are presented. It is shown that low distortion transistor-only SC filters can be realized employing MOSFET gate structures biased in accumulation or strong inversion to implement the capacitors. As a consequence, mixed analog/digital circuits can be fully integrated using CMOS gate arrays. >

Full compatibility of SC (switched-capacitor) filters with VLSI processes has been demonstrated. To this end, the conditions for linear charge and voltage processing have been derived. Considerations on the precision of the transfer function coefficients and on the alternatives for capacitor implementations show the feasibility of high-precision, low-distortion SC filters integrated in any digital MOS process. >

The capacitive gate structures available in digital oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. Experimental and analytical results indicate that the total harmonic distortion (THD) in an adequately biased (2.5 V) gate capacitor can be kept low (THD >