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A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- of high full-well capacity (FWC) per a tap is obtained by employing a supplementary MOS capacitor. 36% of high quantum efficiency (QE) has been achieved by backside scattering technology (BST) and thick silicon process. In addition, demodulation contrast (DC) is improved to 86 % by additional deep photodiode doping process for static potential gradient in a photodiode.

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. The major source of leakage current on NMOS and PMOS devices was different pathways, and it was controlled by reduction of gate poly-Si oxidation thickness and the optimization of LDD implantation process. The load PMOS lifetime under the HEIP stress was over 10 years at 3.5V of operation voltage. The SNM margin was obtained in subthreshold operation region by increase the current of load transistor and compensated for the process variation. Finally, SRAM cell of 0.84 /spl mu/m/sup 2/ of size with 0.1 /spl mu/m design rule was successfully fabricated.

We have demonstrated a fully integrated 64 kb MRAM using 0.24 /spl mu/m CMOS technology. We found that the etching of magnetic tunnel junctions (MTJ) was likely to bring about an electrical short between the top and bottom of an MTJ, and capping MTJs after etching was very effective in preventing the short. Besides, we performed a lot of magnetic transport measurements of magnetic tunnel junctions during the development and found that the magnetization reversal was affected by some geometrical factors of an MTJ.

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.