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Laser Marking is a very common part of many manufacturing processes usually performed at the last stages of production lines after the packaging of goods. The speed of production lines are key determinants of the output capacity of many industries, but their scalability could be hindered by some fundamental limits of current laser marking technologies. In this paper, we review related technologies, their limiting factors, and analyze how future systems could overcome them.

Ajudes: National Key Research and Development Program of "Strategic Advanced Electronic Materials" under Grant 2016YFB0401100 and in part by the NSFC of China under Grant 61274083 and Grant 61334008. Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper providesa comprehensive reviewof the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

In this paper we present a novel method to print paper and cardboard without ink. The method is based on the carbonization of paper by a combination of lasers working on different wavelengths. A prove of concept system is created based on combining existing commercial systems to demonstrate the viability of the method. The results show that no debris is generated and the quality of the mark is superior in terms of contrast and resolution with previously known methods.

The creation of visible changes marked onto object surfaces by laser has become an effective way of coding industrial products. Industrial applications for printing solutions drive the demand for higher speed and higher throughput for in-line digital laser marking. Currently, most laser marking equipment is based on a single laser beam with the corresponding sequential processing that culminates in a performance bottleneck which limits printing production line speed to a de facto barrier of 8 m/s. In this paper, we present a system that overcomes this barrier by using a matrix of laser beams controlled by an embedded high-performance computing platform. The industrialized solutions presented in this paper can print images of 50 to 200 dpi resolution on printing substrates widths ranging from 6 mm to 50 mm, at product line speeds of up to 16 m/s. The analysis we have performed suggests that even higher speeds could be achieved by investing in additional laser beams.

Organic electronics is one of the most promising technologies for creating flexible electronic devices using low temperature plastic compatible processes. However, contact resistances of organic transistors remain one of the most significant hurdles to achieving high performance circuits in this technology. Short channel devices (

In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Specifically, inkjet printing technology has been increasingly applied as advanced deposition technology in the field of printed electronics due to the high flexibility in terms of patterns (mask-less) and materials, and its low cost approach as only a small amount of materials is required in comparison to other solution-based deposition techniques. Our work focuses on the development of Organic Thin Film Transistors (OTFTs) by using organic, inorganic inks and low-cost all-inkjet purely printing process, thus centring the effort in the design, manufacturing and characterization point of view in order to fabricate all-inkjet printed organic integrated circuits. Electrical and morphological characterizations were performed in order to obtain device statistics to investigate the origins of the failures responsible for the low yields. Most of research works are based on laboratory inkjet equipment for manufacturing using single nozzle systems to fabricate small numbers of devices. The variability and mismatch of the printed devices are underrepresented in literature and are key factors towards commercialization of printed electronics.

We report on the development of inkjet-printed thin-film resistors using both organic and inorganic ink formulations. The passive devices were manufactured on flexible polymer substrates in ambient condition without the need for a cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. By using the same manufacturing process, the rapid electrical sintering (RES) method is demonstrated as effective for the fabrication of inkjet-printed, programmable Write-Once-Read-Many (WORM) memories. Several hundred fully inkjet-printed resistors with different parameters were fabricated and subsequently morphologically and electrically characterized with the aim of obtaining statistically significant data. From a manufacturing process viewpoint, the procedures based on inkjet printing herein described are highly attractive: they do not require high temperatures, low pressures, special atmospheric conditions, and any masks, therefore providing a versatile low-cost approach to fabricate passive electrical components and simple circuits useful for the electronic industry. Printing can be carried out at a sufficiently low temperature to avoid damage to the fabric substrate and these devices can be used in a range of applications requiring flexible and conformal devices from embedded passive filters in PCBs to wearable electronics.

This paper presents two main contributions toward efficient VLSI circuits mapped with simple cells: (1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and (2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates. Just as the first information revolution caused by integrated silicon circuits, PE is expected to cause another revolution characterized by the distribution of information systems in all aspects of life. Although the integrated circuits, based on Organic Thin Film Transistors (OTFT), are not meant to compete with the silicon-based high-end industry, their performance have already reached to a level enabling the use of organic technology to an ever-increasing number of emerging applications, such as flexible optical displays, sensors, and low-end microelectronics. Currently, most of the digital integrated circuits are yet designed by specifying the layout of each individual transistor and their interconnections. Full-custom design is extremely labor-intensive, time consuming for complex circuits and it requires advanced computer software in the design process, and several expensive mask sets in the fabrication process. Besides, taking the soft and hard faults at transistor level into account, the yield at system level is expected to be very low, since failure of one transistor causes the entire circuit to fail. This is more important for technologies based in non-crystalline materials (such as silicon) in which deposition and layer formation is more irregular. On the other side, organic electronics is more complex than Printed Circuit Boards (PCB) in the sense that these do not include active devices and do not reach high integration level. Furthermore, similar to any new-born technology, the performance of organic electronic circuits is degraded due to some limitations in technological and materials sides. That being said, the question arises as to whether circuit design techniques can be employed to compensate these bottlenecks so as to meet yield and performance requirements. The work presented in this thesis contributes to overcome the above-mentioned issues by proposing the novel concept of Inkjet-configurable Gate Array (IGA) as a designmanufacturing method for the direct mapping of digital functions on top of new prefabricated structures. IGA brings together the advantages of semi-custom gate array methodology, field-configurability, and fault-tolerance, and adopt it to Application Specific Printed Electronic Circuit (ASPEC), which is the equivalent term to Application Specific Integrated Circuit (ASIC), but for PE. This alternative has two main advantages. Firstly, it allows implementing individual circuit personalization at a very low cost through the best use of additive mask-less digital printing techniques (e.g. Inkjet, Superfine Jet, and etc.) "in the field", thus avoiding the need for One Time Programmable ROM-like (or E2PROM) devices. Secondly, fault tolerance technique allows the adoption of a failure map to use only working transistors for circuit implementation, thus, it helps to obtain high yield circuits out of mid-yield foils.

The objective of the present research is to observe to what extent the stereoscopic effect presents a solution for enhancement of user interactions in the Web context. This paper describes an experiment conducted to detect differences in perception between 2D and 3D graphical user interfaces of an e-Commerce web application. The results of the conducted user study among 39 participants indicate significantly higher performance of the 2D interface in terms of efficiency, satisfaction, and, consequently, overall usability. Therefore, for the studied sample, the stereoscopic effect had mostly negative impact on user interactions. El objetivo de la presente investigación es observar hasta qué punto el efecto estereoscópico es una solución para mejorar la interacción del usuario en el contexto Web. Se describe un experimento llevado a cabo para detectar diferencias de percepción entre las interfaces gráficas de usuario 2D y 3D de una aplicación web de comercio electrónico. Los resultados del estudio de usuarios, llevado a cabo con 39 participantes, indican un rendimiento significativamente más alto de la interfaz 2D en términos de eficiencia, satisfacción y, en consecuencia, facilidad de uso general. Por lo tanto, para la muestra estudiada, el efecto estereoscópico tuvo un impacto mayormente negativo en las interacciones del usuario.

This article describes the web application called S3Doodle. It is an initial example of the combination of a stereoscopic graphical user interface that produces stereoscopic content and is controlled by hand gestures. The web application uses core stereo 3D concepts and implements them with cutting edge technology to create a differentiated experience. We use a spatial input control as an interface that allows us to introduce depth into the created compositions. S3Doodle’s creation is documented, and the experience we had while building it is explained, shedding light on which are the technical decisions behind. We also gather user’s comments from the utilization of the web app. This application serves us as a case study for exploring gestural and stereo interactions, from which we get initial reactions upon which we can provide a better experience for future applications.

In this paper we focus on the creation of a tool that alows us to put stereoscopic depth into a web page. We also explore with an experiment to what extent this stereoscopic depth may control a user's gaze pattern while performing a search task. The tool uses HTML5 to create 3D stimuli compatible with stereo displays. The stimuli created consists of a search engine result page created in a 2D and 3D side by side format. We then test the stimuli with eye tracking equipment and perform a questionnaire that gathers information about participants' opinion towards a stereoscopic 3D experience. While this experiment is a first pilot and more research is needed, it is indicative of user behavior. In this paper we describe preparations for the study, hardware and software tools used to carry out the experiment, and results analysis.

The benefits of stereoscopic vision in medical applications were appreciated and have been thoroughly studied for more than a century. The usage of the stereoscopic displays has a proven positive impact on performance in various medical tasks. At the same time the market of 3D-enabled technologies is blooming. New high resolution stereo cameras, TVs, projectors, monitors, and head mounted displays become available. This equipment, completed with a corresponding application program interface (API), could be relatively easy implemented in a system. Such complexes could open new possibilities for medical applications exploiting the stereoscopic depth. This work proposes a tool for production of interactive stereoscopic graphical user interfaces, which could represent a software layer for web-based medical systems facilitating the stereoscopic effect. Further the tool's operation mode and the results of the conducted subjective and objective performance tests will be exposed.

In this article, we present a drawing toolkit developed to create stereoscopic side-by-side 3D stimuli. The toolkit is based in the HTML5 canvas element and drawing is achieved using intermediate stereo scripting methods that correspond to the ‘2d’ context of the canvas. We include performance marks of the toolkit running on desktop and mobile browsers. Also, a discussion of how the tool is used for implementing a stereo 3D UI is specified.

Creating the layout of an application graphical user interface is an important part of any system development process. Mock-ups, usability studies, focus groups and sketching are techniques that help define this layout and ship the best UI for the required task. But with the addition of 3D depth into the GUI assortment, a gap is exposed when trying to draft the GUI due to the fact that depth cannot be easily represented using traditional 2D methods like paper or existing software. With this article we present a tool that allows designers and developers to draft graphical user interfaces that comply with stereoscopic side-by-side formats. The tool is created using the HTML5 canvas element, in conjunction with the browser’s console to live edit any sketch, and created layouts can be saved and shared in devices capable of showing compatible stereoscopic images.

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (Vth < |5 V|) and a mobility ≈0.1 cm2/(V s). A comparison of identically fabricated transistors shows that devices with coated dielectric have a higher operational stability than those using bare c-PVP. This conclusion is supported by a quantitative study of the threshold voltage shift with time under continuous operation. Long exposure to the ambient atmosphere causes an increase in the threshold voltage strongly dependent on the used semiconducting ink formulation. © 2015 Elsevier Ltd.

The benefits provided by the stereoscopic vision have been thoroughly studied for more than a century. The results of this research state that S3D, when properly implemented, enhances efficiency of different applications. At the same time, the market of 3D-enabled technologies is blooming, revealing new devices to the public. 3D cameras, TVs, projectors, monitors, and mobiles are becoming more and more affordable and are not considered as something exotic anymore. Yet this technology is far from being widely implemented. The scarcity of tools for production of such content along with the absence of proper guidelines establishing the rules for S3D depth implementation could be the main reason. With this work we present a tool for generation of interactive stereoscopic HTML compositions. We describe the tool’s operation mode and expose results of the performance test.

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): l)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

To allow real performance-driven logic synthesis, area, power and delay trade-off should be considered from the very early stages of the synthesis process. Accurate models must be provided for area occupation, delay, and power dissipation. Moreover, the model parameters should be available during all stages of logic synthesis. In this paper we present the models and derive cost functions to calculate their parameters. At the early stages of logic synthesis, generic cell library information and statistical data extracted from real integrated circuits (IC) are used to calculate the model parameters. As the synthesis process progress, technology dependent information becomes available and the model parameters are gradually refined.

With this paper we document an experiment that is defined to test to what extent stereoscopic depth may control a user’s gaze pattern while performing a search task. The experiment consisted in displaying a search engine result page created in a 2D and 3D side by side format, and a questionnaire that gathers information about participants’ opinion towards a stereoscopic 3D experience. While this experiment is a first pilot and more research is needed, it is indicative of user behavior. In this paper we describe preparations for the study, hardware and software tools used to carry out the experiment, and results analysis.

This paper presents the design of a multi-processor system to control a Laser Marking machine. The use of multiple soft-core processors allows to independently control multiple heads that share a single laser beam. We show that with several design decisions we can increase the laser beam utilization factor up to 92%. Besides, we present a multi-soft-core architecture, a particular programming model, and how the system is extended to enable performance analysis.

The emergence of wearable intelligent textile systems with sensors and actuators nodes are integrated into user clothes. Emergency units can benefit from new technologies to improve their performance and security conditions when working exposed to risk situations. In firefighters case is a the system Bluetooth Low Energy (BLE) at 2.4GHz with a watch to show the thermal stress and, in case of exceed healthy level will trigger an alarm to warn the user. In this scenario the design and study of the working conditions of an antenna is a crucial issue for ensuring the communication capabilities of the the whole system. In this work paper we present the design, development and test of a miniature flexible antenna prepared to integrate in the uniforms maintaining the radiation properties although bend or warming. We will see how to minimize the size of the antenna with a antenna PIFA on a Polyethylene Terephtalate (PET) substrate.

Following EU directives on Media Access and Ambient Assisted Living, the broadcasting industry needs to introduce new services in order to guarantee access to all citizens. The article and its conclusions are part of the EU project DTV4ALL, which focuses on some possible broadcasting scenarios for achieving barrier-free television for those with visual impairments. Five enhanced Audiodescription (AD) scenarios were proposed and evaluated: 1) Live streaming Internet TV with AD, 2) AD reception in a group situation, 3) Video on demand over a set-top-box, 4) Video on PC and 5) Podcasts. User evaluation concerning usefulness, quality and usability of the services was assessed using questionnaires. Results of the user evaluation show that not only are AD emerging services technically viable but they are also positively rated by users. Implementation of these services will provide improved access to content, making TV accessible for all.

Ambient Assisted Living Technologies are providing sustainable and affordable solutions for the independent living of senior citizens. In this scenario, telemedicine systems enhance distance patient's health care through interactive audiovisual media at home. Today TV is becoming the main connected device at home. However, Interactive TV applications must be fully adapted, particularly to the available input device: the Remote Control (RC). Despite this adaptation, some tasks are still uncomfortable due to the RC limitations. Therefore, more user-friendly input modalities are strongly desired. Spoken language allows distance hands- and eyes-free operation within the room, providing an intuitive and natural interface. This paper presents some accessibility facilities based on speech technologies for an interactive TV telemedicine service. The specific layout for TV environments, the help of an avatar and the voice navigation will enhance the user access, while the speech-based creation of medical reports reduces dramatically the time physicians need to write reports.

In this article we present a study and the corresponding implementation of low cost printed antennas in the 2,4GHz band. These antennas work with low cost transceivers that give a FR input/output signal in the band of interest. The work is part of a project in the field of sensor networks using technology such as Zigbee or even simpler and cheaper systems. We have focused our attention on parameters such as the antenna impedance, which is very important for achieving maximum power transfer with the transceiver while avoiding adaptation circuits. We are also interested in avoiding balums. We have analyzed these printed antennas in terms of their efficiency and radiation pattern using electromagnetic simulation software. Two structures have been evaluated and compared. The first is a structure derived from a monopole and slot antenna and the second is a printed patch antenna.

This paper presents a method to automatically recognize and model singleand multi-output logic gates out of a switch-level network, even for irregular transistor structures. Resulting subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.

Real-time optical processing is an area of increasing interest in several fields like pattern recognition and inspecting tasks. The development of Spatial Light Modulators (SLMs) capable to display a complex amplitude 2D- distribution in real-time has been very important to obtain real-time optical processors. One of the biggest challenges for improving these processors is to obtain SLMs with a pixel-by-pixel control, which could be easily implemented and fully controlled spatially and with grey-level addressing. Liquid Crystal Displays (LCDs) are inexpensive and suitable SLMs for recognition optical purposes. The LCD panels from the Epson VP100PS videoprojector have been deeply characterized and intensively used as SLMs in optical correlators for pattern recognition. The SLMs can be used in the filter plane as well as in the input plane. If the input image to analyze entails particular requirements in spatial resolution and grey level quantization the response features of the SLM used to display the input image can be critical. In this work we present a full pixel-by-pixel control of the matrix with a PC board. A Field Programmable Gate Array (FPGA) is designed to control a PC board as a prototype to implement a Very Large Scale Integration ASIC driver using the 2.5 microns technology available from the Centro National de Microelectronics (CNM-CSIC, Bellaterra, Spain). The project results in an inexpensive and easy- reconfigurable PC board with the FPGA prototype, and an easy migration to a fully integrated driver of the display.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This paper describes a 12-bit current mode digital to analog converter. Circuit topology uses two arrays of 64 equal current sources, each one generating both the current associated to six bits, corresponding to either MSB or LSB parts. The main novelty of that topology is the method used to limit the maximum current provided by the LSB block, which ensures a monotonic behavior of the system. The circuit has been designed and fabricated using a 0.35 /spl mu/m CMOS process and occupies an area of 0.17 mm/sup 2/.

One of the greatest challenges in the field of printed electronics is the performance stability of the devices fabricated by the different printing technologies e.g. inkjet or gravure printing technology. The performance instability can be defined in terms of the device breakdown or by other effects like the emergence of leakage current under the constant high voltage inputs (especially the dielectric within the transistor architecture). The reasons behind this phenomenon can be various, but the most prominent indication can be detected from the materials used and the deposition methodology. For this purpose the herein work is presented, targeting on the all inkjet-printed organic thin film transistor (OTFT), but keeping the focus on the basic building block for fabricating inkjet-printed OTFTs. In this case it is the metal-insulator-metal (MIM) layer structure. Herein, the MIM structures are inkjet-printed, and then characterized optically and electrically. The dielectric layers for the MIM structures are printed using three different dielectric ink materials either individually 1) Single component system; or in combination with each other as in form of bi-layer stack 2) Multiple component system. The thickness of the printed dielectric layers is varied for these MIM structures. The electrical characterization is performed with respect to current vs. applied voltage and is done for a large number of iterations. The leakage current is of interest and shows a negative and positive trend towards the single component system and multiple component system for the dielectric layers in the MIM characterization structures respectively.

The present work explores the effect of introducing stereoscopic depth to two specific examples of applications. The utilized depth has both an aesthetic and utilitarian function. One case explores a 3D garment catalog, and gives the user the task to rate garments. The second use case is a ‘Pairs’ game in which completing the game itself is the task. In total, effectiveness, efficiency, usability, desirability and gaze patterns were compared between monoscopic and stereoscopic versions of both applications. Time to complete the relevant task did vary, but efficiency, usability, and visual perception did not change. Desirability and eye patterns did differ. This behavior is important to acknowledge in order to better design experiences that utilize stereoscopic images.

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.