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The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.

The multilayer ceramic composites (MLC) consist of two ceramic materials insoluble in each other and sequentially piled in a symmetric manner whereas they can be divided into two groups: multilayer composites with weak interfaces and composites with strong interfaces. The graphene added multilayer ceramic sandwich (GMCS) composite was developed. The multilayer stack of Si3N4 with 5 and 30 wt% graphene addition were stratified in sandwich structure. So formed multilayer stacks with 5 and 7 layers were sintered by hot issostatic pressing (HIP). The homogenity of graphene addition, the effect of layered structures and the position of layers with lower and higher graphene content on the final properties were studied.

The stress related shifts of transistors are measured by precise stress application with a newly designed in-situ four-point bending (4PB) system. A test board including a flip chip packaged test vehicle is loaded with uniaxial stress. The test vehicle contains dedicated ring oscillator circuits fabricated in the 22 nm FDSOI technology node, used to evaluate the effects of thermo-mechanical stress on the characteristics of CMOS devices. Finite element simulation provides insight into the originated stress values in the board, package, and active devices during mechanical loading. Considering the bending caused stress in the devices and the specific layout of the circuits, the directional frequency shifts of the circuits under stress are derived. These shifts are compared with a previous indentation study, which has been developed to induce very localized loads. The comparison aims for verification of the indentation approach to study directional stress related effects as well as very localized effects in chip stacks.

With the increasing amount of on-chip interconnects and continuous down-scaling, electromigration will play a more critical role especially for automotive reliability, which requires high statistical confidence. In confined metal lines, tensile stress builds up at the cathode side before void nucleation; compressive stress builds up at the anode side. A critical stress is required for EM-induced void formation to occur. Proper understanding of the critical stress is crucial for boosting interconnect RC performance, yet guaranteeing robust electromigration reliability. This study aims to characterize the short length effect and physical degradation behavior with a modified Wheatstone Bridge structure to significantly increase the statistical confidence.

The stress-related change in the characteristics of transistors manufactured in the 22 nm fully depleted silicon on insulator (FDSOI) CMOS technology node is studied with advanced experimental indentation setups. Precisely, NAND and NOR ring oscillator circuits are used to monitor the strain-caused mobility deviations in the silicon transistor channels. Piezoresistive coefficients for strained silicon are calculated from the experimental indentations data using spherical and cylindrical tip geometries. In contrast to spherical tips, the cylindrical indentation tips enable to induce the stress more selectively into a desired direction. To set up the experimental details appropriately, finite element (FE) simulations have been used. Additionally, FE method (FEM) studies are conducted to compute the quantitative strain values in the silicon transistor channels as a function of contact load as well as chip and tip geometries. Using the signal deviations of the RO circuits subjected to strain from spherical and cylindrical indentation, a set of equations using the linearized piezoresistive model are created to determine the directional piezoresistive coefficients.

Silicon nitride–zirconia–graphene composites with high graphene content (5 wt.% and 30 wt.%) were sintered by gas pressure sintering (GPS). The effect of the multilayer graphene (MLG) content on microstructure and fracture mechanism is investigated by multi-scale and in-situ microscopy. Multi-scale microscopy confirms that the phases disperse evenly in the microstructure without obvious agglomeration. The MLG flakes well dispersed between ceramic matrix grains slow down the phase transformation from α to β-Si3N4, subsequent needle-like growth of β-Si3N4 rods and the densification due to the reduction in sintering additives particularly in the case with 30 wt.% MLG. The size distribution of Si3N4 phase shifts towards a larger size range with the increase in graphene content from 5 to 30 wt.%, while a higher graphene content (30 wt.%) hinders the growth of the ZrO2 phase. The composite with 30 wt.% MLG has a porosity of 47%, the one with 5 wt.% exhibits a porosity of approximately 30%. Both Si3N4/MLG composites show potential resistance to contact or indentation damage. Crack initiation and propagation, densification of the porous microstructure, and shift of ceramic phases are observed using in-situ transmission electron microscopy. The crack propagates through the ceramic/MLG interface and through both the ceramic and the non-ceramic components in the composite with low graphene content. However, the crack prefers to bypass ceramic phases in the composite with 30 wt.% MLG.

The impact of strain, induced by nanoindentation, on integrated circuit performance is measured. Localized strain caused by chip- package interaction alters the charge carrier mobility in the transistor channel due to the piezoresistive effect. Instrumented indentation enables to induce controlled localized loads with high lateral precision, and it is used to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in 22 nm FDSOI technology are used as a sensor to monitor the strain effect on transistor performance. Novel tip geometries provide insight into the direction dependent strain impact. Strain/stress fields at transistor level are determined by complementary FEM simulation. Board bending experiments with uniaxial stress/strain conditions are performed to verify the approach. The established correlation of mechanical load and device performance is used to provide an estimate for the effect of package related stress on transistor performance.

The paper is devoted to the study of microstructural and magnetic properties of the Fe-based amorphous ribbons after interference pulsed laser heating. The ternary amorphous alloy FeSiB, as well as the multi-component alloys FeCuSiB and FeCuNbSiB, was subjected to laser pulses to induce crystallization in many microislands simultaneously. Structure and properties changes occurred in laser-heated dots. Detailed TEM analysis from a single dot shows the presence of FeSi(α) nanocrystals in the amorphous matrix. The FeSiB alloy is characterized after conventional crystallization by a dendritic structure; however, the alloys with copper as well copper and niobium additions are characterized by the formation of equiaxed crystals in the amorphous matrix. Amorphous alloys before and after the laser heating are soft magnetic; however, conventional crystallization leads to a deterioration of the soft magnetic properties of the material.

Chip-package interaction-caused mobility degradation in CMOS transistors is a critical degradation mechanism for microelectronic devices. An approach based on nondestructive indentation is applied to induce highly localized stress fields. Strain-sensitive ring oscillator circuits are integrated to monitor parametric deviations during mechanical loading. In this study, the indentation technique is used to investigate the impact of the chip layout and geometry of a flip chip-packaged test chip. Complementary FE simulation provides a better understanding of the relevant stress-strain fields and enables a comparison of the parametric circuit deviations within a dedicated stress tensor. The results demonstrate the capability to study the stress-strain distribution in microelectronic devices during external loading with indentation and to determine its impact on transistor degradation.

A novel method to quantify and predict the material contrast using Backscattered Electron (BSE) imaging in Scanning Electron Microscopy (SEM) is presented while using low primary electron beam energies (Ep). In this study, the parameters for BSE imaging in Low Voltage Scanning Electron Microscopy (LVSEM) are optimized for the layer system Al0.22Ga0.78N/GaN, which is typically used in High Electron Mobility Transistors (HEMTs). The layers are imaged at high resolution and the compounds are identified based on the quantitative BSE material contrast between Al0.22Ga0.78N and GaN. The quantification process described in this study is based on an analytical description that predicts the material contrast using a function that correlates the effective backscattering coefficient (η) with the atomic number Z.

In this study, the effect of microstructure of porous nickel electrode on the performance of high temperature fuel cell is investigated and presented based on a molten carbonate fuel cell (MCFC) cathode. The cathode materials are fabricated from slurry consisting of nickel powder and polymeric binder/solvent mixture, using the tape casting method. The final pore structure is shaped through modifying the slurry composition - with or without the addition of porogen(s). The manufactured materials are extensively characterized by various techniques involving: micro-computed tomography (micro-XCT), scanning electron microscopy (SEM), mercury porosimetry, BET and Archimedes method. Tomographic images are also analyzed and quantified to reveal the evolution of pore space due to nickel in situ oxidation to NiO, and infiltration by the electrolyte. Single-cell performance tests are carried out under MCFC operation conditions to estimate the performance of the manufactured materials. It is found that the multi-modal microstructure of MCFC cathode results in a significant enhancement of the power density generated by the reference cell. To give greater insight into the understanding of the effect of microstructure on the properties of the cathode, a model based on 3D tomography image transformation is proposed.

A well-documented effect of the mechanical stresses generated by 3D IC packaging on the performance of electrical circuits, in some cases leading to their parametric failure, can be controlled by means of stress assessment EDA tools. Verification and calibration of the layout engineered stress models are traditionally performed on the basis of electrical data demonstrating the stress induced changes in transistors' drain currents. This paper demonstrates the validity of such an approach in the case of chip-package interaction (CPI) induced stresses. Through-silicon vias (TSV) were chosen in this study as a well-controlled stress source. Specially designed test-structures were used for measurements of TSV-induced strains in FET channels by means of the TEM/CBED (Transmission Electron Microscopy/Convergent Beam Electron Diffraction) technique. Measured strains were used for calibrating the developed finite-element analysis (FEA) model of TSV-induced stress. The calibrated stress model was employed for calculating the TSV induced drain current changes in the nearby devices in the test structures designed for electrical measurements. The demonstrated good fit between the calculated and measured current changes validates the use of electrical measurements for calibrating CPI stress assessment models.

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

A novel nanoindentation technique is used to investigate the influence of mechanical strain on integrated circuit performance. The approach aims to investigate localized stress fields caused by Chip-package interaction and resulting reversible transistor parameter deviations due to the piezoresistive effect. Nanoindentation enables controlled localized loads with high lateral precision and to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in the 22 nm FDSOI technology node enable a high sensitivity to mechanical load. They were used to monitor the strain effect on the transistors performance. Complementary FEM simulations provide deeper insight into the occurring stress tensor components and their respective impact. The results give an estimation for package related stress influences on devices based on the established correlation of mechanical load/strain and devices performance.

A laboratory-based X-ray microscope is used to investigate the 3D structure of unstained whole pollen grains. For the first time, high-resolution laboratory-based hard X-ray microscopy is applied to study pollen grains. Based on the efficient acquisition of statistically relevant information-rich images using Zernike phase contrast, both surface- and internal structures of pine pollen - including exine, intine and cellular structures - are clearly visualized. The specific volumes of these structures are calculated from the tomographic data. The systematic three-dimensional study of pollen grains provides morphological and structural information about taxonomic characters that are essential in palynology. Such studies have a direct impact on disciplines such as forestry, agriculture, horticulture, plant breeding and biodiversity.

Energy-filtered backscattered electron imaging in a scanning electron microscope is performed on a blend of zinc-phthalocyanine (ZnPc) and fullerene (C60), whose morphology is characterized using a novel energy selective backscattered (EsB) electron detector in combination with low acceleration voltages for the primary electrons. Such blends are used as an active layer of organic solar cells in bulk heterojunction architectures. The key to optimizing the solar cell performance is understanding the morphology of the blend components. Comparing the results to TEM micrographs, the EsB detector allows for a simple and fast identification of the phases in the blend. The relevance of the findings for applying ZnPc–C60 blends in solar cells is also discussed.

The influence of the various content of the multilayered graphene (MLG) on the structural and mechanical properties of the final bulk porous silicon nitride-zirconia (Si3N4-ZrO2) based ceramics was investigated. The ceramic composites were prepared in the form of the laminated structure with different (5-30-5 wt% and 30-5-30 wt%) MLG content by hot isostatic pressing. Homogeneous distribution of the MLGs, a completed phase transition from α to β-Si3N4 in case of 5 wt% MLG have been observed. The structural examinations revealed that the multilayered graphene and zirconia particles owing to their different sizes and shapes influenced the porous microstructure evolution and the related mechanical properties of the composites. The sandwich structures enhanced the mechanical properties compared to reference ceramic with 30 wt% MLG. The position of the layer with higher graphene content, high ratio of α/β phase of Si3N4 and higher porosity had crucial effect on the final mechanical properties.

Electromigration-induced stresses play a major role in the analysis and the explanation of this important reliability degradation mechanism. It is generally assumed that the directed atomic transport generates tensile stress at the cathode end of an interconnect structure while compressive stress is generated at the anode end. At short on-chip metal interconnect lengths, the electromigration-induced stress gradient between the cathode and the anode counteracts the primary electromigration effect (i.e. the directed atomic transport), leading to the well-known Blech effect. In this study, Wheatstone bridge devices with 4 × 100 Cu interconnects are used in a configuration which is different from the usual application. All 400 Cu interconnects per bridge are wired in a parallel/series arrangement without the regular resistance tapping, disabling the original approach of a high detection probability of early failures. Instead, a very high statistical sampling for measurements of resistance increases occurring in each individual interconnect can be achieved, leading to an almost “perfect” resistance increase behavior as a function of stress time at elevated temperatures. Furthermore, at conditions close to, but above the critical current density • length product (jL)c, the linear drift portion as well as saturation effects at later times can be used to evaluate the critical product with statistical significance. Selecting the robust contact/M1 interface in a first proof-of-concept analysis, a value of (jL)c = (510 ± 110) mA/μm is determined for 40 μm long Cu(Mn) M1 interconnects with 45 nm width and 100 nm height.

This chapter discusses the application of scanning and transmission electron microscopy techniques, X-ray microscopy, as well as scanning probe microscopy for physical failure analysis. With the scaling-down of transistor features and interconnect dimensions and with the introduction of new processes and materials, physical failure analysis becomes more and more an essential task to exclude both yield-limiting process irregularities and reliabilityrelated failures in the semiconductor industry. Advanced imaging tools and techniques are needed to ensure high manufacturing yield and product reliability. Physical failure analysis is an essential task to exclude both yield-limiting process deviations and reliability-related failures in integrated circuit (IC) manufacturing industry. Its goal is to determine the root cause of failures or parameter deviations as a prerequisite for corrective actions. Polysilicon Gate Roughness, control of the transistor gate critical dimension with nanometer accuracy is a top priority task for leading-edge IC manufacturing.

High-resolution imaging of crack opening and propagation in 3D structures to study the fracture behaviour of materials requires new experimental setups. In this report, we describe a novel technique that provides in-situ 3D visualization of crack evolution with high resolution during mechanical loading of multi-component materials: a micro double cantilever beam (micro-DCB) test in an X-ray microscope. We demonstrate that crack opening and propagation can be visualized (in-situ) in the X-ray microscope with a spatial resolution of about 100 nm. For this experiment, micro-DCB samples were prepared to a thickness that was X-ray transparent in the direction normal to the crack front. During the micro-DCB experiment, the load is applied perpendicular to the optical axis of the X-ray microscope while images are collected with phase contrast imaging. The method is validated for a synthetic polymer, Nafion® (DuPont) with dispersed platinum particles. The proof-of-concept experiment demonstrates that sub-micron cracks can be visualized non-destructively, and that the in-situ micro-DCB test allows to study crack opening and propagation in materials. The technique offers several benefits over existing methods and is applicable across a range of disciplines, including materials science (e.g. composites), microelectronics, and life sciences (e.g. tissue, bones).

Laboratory transmission X-ray microscopy with a spatial resolution of about 100 nm was used to image 3D interconnect structures and failures in microchips during mechanical loading, applied by a microDouble Cantilever Beam (micro-DCB) test. High-resolution 3D image sequences based on nano X-ray computed tomography (nano-XCT) are used to visualize crack opening and propagation in fully integrated multilevel on-chip interconnect structures of integrated circuits. The nondestructive investigation of sub-micron cracks during the in-situ micro-DCB test allows one to identify the weakest layers and interfaces, to image delamination along Cu/dielectric interfaces (adhesive failure) and fracture in dielectrics (cohesive failure), as well as to evaluate the robustness of Backend-of-Line stacks against process-induced thermomechanical stress.

High‐resolution computed X‐ray tomography (XCT) is applied in this study to characterize the microstructure of Molten Carbonate Fuel Cell (MCFC) cathodes after operation, where a ""virgin cathode"" formed by porous nickel has been in situ oxidized and infiltrated by liquid electrolyte. This technique extends state‐of‐the art methodology to characterize pores such as porosity analysis using Mercury porosimetry. XCT enables 3D imaging of the internal structure of the electrodes including all components present at the cathode side, particularly NiO, pores, and electrolyte. The quantitative 3D microstructure analysis based on high‐resolution XCT provides topological information for each component and their mutual spatial distribution, which is significant for the enhancement of the MCFC performance. In particular, volume fraction, specific surface area, continuity of each phase, as well as the Triple Phase Boundary (TPB) density are calculated from the experimental data. The results indicate that superior properties of the multi‐modal pore sized cathode, used in this study, can be attributed to the formation of three self‐interpenetrating networks of pathways for the transport of gasses, electrons, as well as ions throughout pores, NiO, and electrolyte, respectively.

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.

The time dependent dielectric breakdown (TDDB) in copper/ultra-low-k on-chip interconnect stacks of integrated circuits has become one of the most critical reliability concerns in recent years. In this paper, a novel experimental in situ microscopy approach using transmission X-ray microscopy (TXM) and scanning transmission electron microscopy (STEM) is proposed to study TDDB degradation and failure mechanisms. It combines electrical testing and imaging techniques. Low-dose bright field (BF) STEM inserting a small condenser aperture is chosen to reduce the beam damage of the dielectric material, while the electron spectroscopic imaging technique is used for the chemical analysis to detect the migration path of Cu atoms. This new experimental approach will contribute to an improved understanding of the TDDB effect.

Focused Ion Beam (FIB) milling is a widely used and important technique to prepare Transmission Electron Microscopy (TEM) lamella samples. However, it unavoidably introduces contamination in the samples like implanted ions. While the conventional ion-solid simulation model, Binary Collision Approximation (BCA), is unable to describe the FIB process, a dynamic BCA model is used in this study to predict the level of Ga implantation along the substrate depth. The FIB process involves significant material transport and local composition alteration, which requires a dynamic model for simulation. To validate the dynamic BCA model's application on simulating the FIB process, atomic level composition analysis Atom Probe Tomography (APT) is performed on Ga FIB processed silicon samples. The experimental data confirm that the dynamic BCA model is capable to predict FIB induced Ga ion implantation in silicon samples.

The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance and reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount of elastic anisotropy, particularly for TSVs with very small diameters. The elastic anisotropy manifests itself in terms of different Young's moduli in different directions and results in orientation-dependent stress distributions. The copper anisotropy in TSVs is measured, and the impact on stress-induced mobility variation and structural reliability is examined using an advanced technology computer-aided design simulator. It is observed that both the charge carrier mobility and the structural reliability are affected by the anisotropy and its orientation. The copper anisotropy effects studied here become more prominent for TSVs with small diameters and/or large aspect ratios, and need to be assessed thoroughly in order to design robust 3-D structures.

Visualization of voids and copper extrusion in copper-filled through-silicon vias (TSVs) under different annealing conditions is greatly enhanced using X-ray microscopy. In addition, the dimensions of the TSVs after Cu deposition can also be measured by 3D reconstruction. Surface inspection found mushroom defects on the top of TSVs after deposition of the etch stop layer, forming a small bump on top of the TSV. The ~50nm etch stop layer is part of the dielectric stack used before metal 1 is deposited on top of the TSVs. The TSVs are annealed, then undergo chemical mechanical polishing (CMP) before the etch stop layer is deposited at 350^oC. It is assumed that after CMP the etch stop layer on top of the TSVs is planar. However, cross-sectional scanning electron microscopy (XSEM) shows mushroom defects but no particles at the interface of the TSV and the etch stop layer. This study investigates the changes in copper extrusion and induced voiding that result from different annealing temperatures. Round TSVs [email protected] deep and [email protected] in diameter were filled with copper by electrochemical deposition (ECD), followed by chemical mechanical polishing and pre-annealing to 150^oC for one hour. Based upon the material properties of TSVs, the high density copper absorbs photon energy more strongly than silicon or air. This results in good contrast within the copper-filled vias when X-ray micrographs are taken and allows voids within the material to be seen. A lab-based X-ray microscope with 8Kev X-ray energy allows a penetration of [email protected] into the silicon. Consequently, sample preparation requires wafers to be backside polished from an initial thickness of [email protected] to

The availability of high-brilliance X-ray sources, high-precision X-ray focusing optics and very efficient CCD area detectors has contributed essentially to the development of transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) with sub-50 nm resolution. Particularly, the fabrication of high aspect ratio Fresnel zone plates with zone widths approaching 15 nm has contributed to the enormous improvement in spatial resolution during the previous years. Currently, Fresnel zone plates give the ability to reach spatial resolutions of 15 to 20 nm in the soft and of about 30 to 50 nm in the hard X-ray energy range. X-ray microscopes with rotating anode X-ray sources that can be installed in an analytical lab next to a semiconductor fab have been developed recently. These unique TXM/XCT systems provide an important new capability of nondestructive 3D imaging of internal circuit structures without destructive sample preparation such as cross sectioning. These lab systems can be used for failure localization in micro- and nanoelectronic structures and devices, e.g., to visualize voids and residuals in on-chip metal interconnects without physical modification of the chip. Synchrotron radiation experiments have been used to study new processes and materials that have to be introduced into the semiconductor industry. The potential of TXM using synchrotron radiation in the soft X-ray energy range is shown for the nondestructive in situ imaging of void evolution in embedded on-chip copper interconnect structures during electromigration and for the imaging of different types of insulating thin films between the on-chip interconnects (spectromicroscopy).

We have investigated silicon–germanium (SiGe) line structures employing metallic apertures in combination with Raman spectroscopy to obtain high-spatial strain resolution below the diffraction limit. The apertures were cut into specifically shaped electrochemically etched tungsten tips, which were adjusted within the Raman laser beam on the sample surface by a tuning fork atomic force microscope. With this setup, line structures on patterned SiGe films with a center-to-center distance down to 200 nm were resolved in the Raman scans, evidently indicating a resolution clearly below the far-field Raman resolution of about 600 nm for the used instrument. This setup allows improved local strain analysis by Raman spectroscopy and shows potential for further near-field Raman applications. Copyright © 2008 John Wiley & Sons, Ltd.

The effect of the nitrogen content on the thermal stability and degradation mechanisms of Ta–Si–N diffusion barriers was studied using methods that prove Cu interdiffusion. On the one hand, glancing angle X-ray diffraction was applied to detect Cu 3 Si formation after annealing of Cu/Ta–Si–N/Si layer stacks. On the other hand, a combined secondary ion mass spectroscopy and transmission electron microscopy analysis of Ta–Si–N/Cu/Ta–Si–N/SiO 2 /Si samples was performed. For a detailed investigation of the microstructure evolution, the crystallization behavior of both Cu-capped and uncapped Ta–Si–N/Si samples was analyzed using X-ray diffraction. In the case of an uncapped Ta 73 Si 27 film, Si interdiffusion from the substrate precedes the layer crystallization. The substrate influence on the crystallization process decreases with increasing N content x N of the Ta–Si–N layer. Using Cu/Ta–Si–N/Si samples, a critical temperature for Cu silicide formation was determined. This temperature increases with increasing N content of the Ta–Si–N barrier. In the case of Ta–Si–N films with x N > 25 at.%, Cu interdiffusion into the substrate occurs before a significant barrier crystallization is observed. For Ta–Si–N layers with x N ≤ 25 at.%, no indications for Cu diffusion before crystalline phase formation were detected.

Both in situ microscopy experiments at embedded inlaid copper interconnect structures and numerical simulations based on a physical model are necessary to develop on-chip interconnect systems with a high immunity to EM-induced failures. In future, the copper microstructure will become more critical for interconnect reliability since interfaces will be strengthened, and consequently, they will not be the fastest pathways for the EM-induced mass transport anymore. As a consequence, copper microstructure characterization becomes increasingly important, and microstructure data have to be implemented into the numerical simulation. The described physical model will help to provide a closer link between the microstructure and the EM lifetime of copper interconnects.

Reservoir effect in dual-damascene Cu interconnect structures caused by electromigration was studied by in situ secondary electron microscopy (SEM). Electromigration-induced void nucleation and apparent void movement in opposite direction to electron flow along the Cu/SiN"x interface was found to be responsible for the observed reservoir effect. The observed void evolutions seem to be contrary to current understanding of reservoir effect based on maximum tensile stress developed at the cathode via and on current gradient induced vacancy flux. The influence of the observed reservoir effect on electromigration mechanisms is discussed in detail.

The influence of N content on the crystallization behavior of initially amorphous Ta–Si–N diffusion barriers deposited with a thickness of 10 nm between Cu and SiO 2 was investigated by means of glancing angle X-ray diffraction (XRD), glow discharge optical emission spectroscopy (GD-OES), transmission electron microscopy (TEM), and graphite furnace atomic absorption spectrometry (GF-AAS) after annealing for various times at a temperature of T an =600 °C. For a Ta 73 Si 27 film, only Ta silicide phases (Ta 5 Si 3 , Ta 2 Si) are formed, whereas all barriers containing nitrogen crystallize primarily into a Ta nitride. Si is not incorporated into this phase but diffuses mostly into the Cu film. Although the crystalline Ta nitride grows mainly within the original barrier region, it does not form a continuous layer. For barriers with a N content x N ≥25 at.%, the annealing time necessary to start the crystallization increases and the formed Ta nitride phases become N-richer (Ta 2 N→Ta 5 N 6 ). A Ta 30 Si 18 N 52 layer maintains its amorphous structure even after annealing for t an =100 h. With increasing N content in the barrier, the thermal stability against Cu diffusion is improved.

Due to the continuing downscaling of transistor and interconnect structures in microelectronic products, today only transmission electron microscopy (TEM) is capable of on-product analysis of the smallest structures with sufficient spatial resolution. However, finite specimen thickness complicates the interpretation of conventional TEM images. Electron tomographic three-dimensional object reconstruction is a promising approach to overcome this limitation. We applied this technique for the first time to characterize Cu interconnect Ta-barrier/Cu-seed layer stacks deposited under different conditions. Their roughness and step coverage becomes clearly visible in the reconstructions. Current possibilities and limitations of this technique as well as future requirements are discussed.

Microstructure, phase composition and interface properties of 10- and 50-mm thick CVD-deposited W-N layers covered with Cu were investigated. Phase formation and structural changes of the layer stacks occurring at elevated temperatures (450-600 °C) were correlated. The initially amorphous barriers undergo an abrupt crystallization between 550 °C/1 h and 600 °C/1 h anneals in vacuum. Further annealing at 600 °C up to 16 h leads to changes in the layer configuration such as N redistribution and Cu agglomeration. No signs of significant Cu diffusion through the barriers were observed for the performed anneals up to 600 °C/16 h.

In this work, we show the doping of graphene most likely from heteroatoms induced by the substrate using Raman spectra, x-ray photoelectron spectroscopy, energy dispersive x-ray spectroscopy and ab initio molecular dynamics (MD) simulations. The doping of graphene on a highly boron-doped silicon substrate was achieved by an annealing at 400 K for about 3 h in an oven with air flow. With the same annealing, only the Raman features similar to that from the pristine graphene were observed in the freestanding graphene and the graphene on a typical Si/SiO2 wafer. Ab initio MD simulations were performed for defected graphene on boron-doped silicon substrate at several temperatures. All vacancy sites in the graphene are occupied either with B atoms or Si atoms resulting in the mixed boron-silicon doping of the graphene. The MD simulations validated the experimetal finding of graphene doped behavior observed by Raman spectrum. The electronic structure analysis indicated the p-type nature of doped graphene. The observed doping by the possible incorporation of heteroatoms into the graphene, simply only using 400 K annealing the boron-doped Si substrate, could provide a new approach to synthesize doped graphene in a more economic way.

Diffractive optics for hard X-rays feature superior properties in terms of resolution and efficiency, if volume diffraction effects are exploited all-over the aperture. For multilayer Laue lenses, preferably a wedged geometry is required to obtain this effect. We present an approach utilizing an additional stress layer to realize the necessary geometrical modifications where each lens can be customized to a selected photon energy independently of the given multilayer deposition. The quality of the deposition of the stress layer is evaluated using a laboratory X-ray microscope prior to its application at synchrotron radiation facilities with a special approach to measure the relative layer tilt at high spatial resolution.

Time-Dependent Dielectric Breakdown (TDDB) in the Backend-of-Line (BEoL) stack has become one of the most important failure mechanisms for state-of-the art integrated circuits and threatens the long-term reliability of advanced semiconductor products. The continuous reduction in the BEoL feature sizes, resulting in continuously smaller spacing between interconnects, along with a slower pace in the reduction of the operational voltages, has led to significantly increased electrical fields. In addition, the introduction of low-k and ultra-low-k (ULK) materials has complicated the situation even more, since lifetimes for those materials are typically several decades shorter than for traditionally used SiO2. While the reliability community has mostly adopted the square-root-E model for backend dielectric failure and has abandoned the more conservative linear-E-model, major questions about the true physical mechanism of dielectric failure, such as the role of Cu, still exist. Within the context of "More than M...

We demonstrate full-field X-ray microscopy using crossed multilayer Laue lenses (MLL). Two partial MLLs are prepared out of a 48 mm high multilayer stack consisting of 2451 alternating zones of WSi2 and Si. They are assembled perpendicularly in series to obtain two-dimensional imaging. Experiments are done in a laboratory X-ray microscope using Cu-Ka radiation (E = 8.05 keV, focal length f = 8.0 mm). Sub-100 nm resolution is demonstrated without mixed-order imaging at an appropriate position of the image plane. Although existing deviations from design parameters still cause aberrations, MLLs are a promising approach to realize hard X-ray microscopy at high efficiencies with resolutions down to the sub-10 nm range in future.

Thin film and interface characterization are necessary in semiconductor industry to ensure high yields and the required reliability of the products. Particularly, the analysis of layer stacks is a challenging task. Transmission electron microscopy (TEM) essentially contributes to layer stack analysis in microelectronic products. Capabilities and limits of analytical TEM techniques as well as advanced TEM sample preparation techniques are discussed for front-end (MOS transistor) and back-end (interconnect) structures. Typical examples for advanced microprocessor devices are shown.

In situ electromigration experiments were carried out to study electromigration-induced failure in the upper and lower layers in dual-damascene Cu test structures. The observations revealed electromigration-induced void movement along the Cu/dielectric cap interface. It supports the premise that Cu∕Si3N4 interface acts as the dominant electromigration path. However, the observed void nucleation occurs in the Cu∕Si3N4 interface at locations which are far from the cathode, and void movement along the Cu∕Si3N4 interface in opposite direction of electron flow eventually causes void agglomeration at the via in the cathode end. The different electromigration behaviors of the upper and lower layer dual-damascene structures are discussed.

Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:Interconnect functions, characterisations, electrical properties and wiring requirements Low-k materials: fundamentals, advances and mechanical properties Conductive layers and barriers Integration and reliability including mechanical reliability, electromigration and electrical breakdown New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.

Quantitative time-resolved x-ray microscopy mass transport studies of the early stages of electromigration in an inlaid Cu line/via structure were performed with about 40 nm lateral resolution. The image sequences show that void formation is a highly dynamic process, with voids being observed to nucleate and grow within the Cu via and migrate towards the via sidewall. Correlation of the real time x-ray microscopy images with postmortem high voltage electron micrographs of the sample indicates that the void nucleation occurs at the site of grain boundaries in Cu, and that the voids migrate along these grain boundaries during electromigration.

Analysis of samples from 3D integration, packaging and joining technologies more often than ever requires the removal of large amounts of material to access deeply buried target structures. Until now, such sample preparation has been achieved using demanding and slow techniques, such as metallographic cross-sectioning, or focused ion beam (FIB) milling. A new tool that combines pulsed laser ablation and FIB milling now allows precise target preparation of deeply buried features in a more efficient way.

In this paper, a scanning thermal microscopy (SThM) module with a modified Wheatstone bridge is presented. It is intended to be used with a novel four-terminal thermoresistive nanoprobe, which was designed for performing thermal measurements in standard static-mode atomic force microscopes. The modified Wheatstone bridge architecture is also compared to a Wheatstone bridge and a Thomson bridge in terms of their temperature measurement sensitivities. In fixed conditions, they are found to be (7.05 ± 0.04) μV K−1 for the modified Wheatstone, while (5.43 ± 0.06) μV K−1 for the Wheatstone and (0.91 ± 0.09) μV K−1 for the Thomson bridge. The usability of the three set-ups with four-terminal nanoprobes is also discussed. The design of devices included in the module is presented and the noise level of the modified Wheatstone bridge is estimated. A proportional–integral–derivative controller for active-mode SThM is also introduced.

The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40x lifetime improvement with a small lifetime variation (σ=0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the M2 level for both with and without the CoWP cap. The EM results showed that, for both caps, the Cu lines with the large grain structure had a longer EM lifetime compared with the small grain structure, and the EM enhancement of the metal cap was reduced for the small grain structure. Failure analysis revealed two failure modes for the SiCN cap, with void formation either at the via corner or in the trench away from the via; on the contrary, voids mostly formed several microns away from the via for the large grain CoWP cap. The difference in voiding locations for the two caps was attributed to the different interfacial mass transport rate. Implications of scaling effect on EM reliability were also discussed.

A force‐sensor technique was developed to determine small forces in‐situ in a scanning electron microscope (SEM), enabling to investigate elastic and plastic deformation modes and corresponding critical strains in single silicon lamellae. Large elastic deformations were obtained, matching with modeling of the Si deformation behavior by finite element analysis. This technique is shown to be applicable also to copper structures obtained after filling of the space between the Si lamellae and subsequent etching. The obtained mechanical properties of the structures on a nanoscale are important for the design of present and next‐generation microprocessors.

Conical dark‐field (CDF) analysis in the transmission electron microscope is introduced as a suitable method for characterizing small Cu grains in advanced interconnect structures. With a proven spatial resolution in the

Continual scaling of on‐chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three‐dimensional (3‐D) integration with through‐silicon‐vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermo‐mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3‐D interconnects. This paper examines the effects of thermally induced stresses on interfacial reliability of TSV structures. First, three‐dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi‐analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady‐state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties are discussed.