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The self-assembly layer consisting of fusion protein is investigated in molecular-scale for the construction of bioelectronic device. Cytochrome b562 and green fluorescent protein were used as an electron acceptor and a sensitizer in the molecular layer by mimicking the photosynthesis. Self-assembled monolayer of fusion protein was formed on Au coated glass. The formation of fusion protein layer onto the Au substrate was observed by the surface plasmon resonance measurement. The surface of fusion protein layer was observed and analyzed by the scanning tunneling microscopy observation. For embodiment of the molecular electronic device, molecular arrays of fusion protein SA layer were formed by micro contact printing. Surface charge distribution of fusion protein SA layer was measured to confirm an electrical conductivity by electrostatic force microscopy observation.

We estimated the process margins of various cell structures and process problems for full chip process under extremeresolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtainedthe fme pattern and wider process margin using simulation and experiment. From our experiment, we should use as highernumerical aperture (NA), smaller R and smaller r as possible to reduce critical dimension (CD) difference between denseand isolated patterns. Process margins are obtained more than 8% exposure latitude (EL) and 0.5 tin depth of focus (DOF)for each cell. However, we can consider using of attenuated phase shift mask (PSM) to improve the exposure and DOFmargin. We fmd that real full chip process induces the critical problems such as isolated line (I/L) and space (L'S) patternvariation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects playa role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and USpattern for various exposure conditions is almost 4Onm or more compared to line and space (L/S) pattern. These phenomenaare becoming the critical issue to fulfill the full chip process of l3Onm lithography. By optimizing mask error effect,isolated and dense pattern bias (ID bias), and OAI, we can achieve l3Onm technology with 248nm KrF lithography.KEYWORDS : KrF, Design rule, ID bias, OAI, Full chip process, High NA, Process margin

As the design rule of device shrinks below O.14j.tm, the higher resolution is required for real device application.With smaller feature size below 0. 14.tm, the lower coating thickness of resist is essential because of the patterncollapse issue at the high aspect ratio. However, the lower resist thickness induces the problem of etch selectivitydue to the limited etch resistance of resist. In this study, the method of electron beam stabilization has beenapplied for improving the etch selectivity ofresist patterns having an aspect ratio less than 3 : 1. With applying theelectron beam stabilization, the Deep-UV photoresists based on the chemical structures of Acetal (AS1O6) andEscap (UV82) types have been evaluated in the respect of etch selectivity as the functions of an electron beamdose and etch condition. The metal etch rate reductions of 20 percent and 26 percent have been occurred for theresists of Acetal and Escap type, respectively, at 2OOOtC/cm2. And the thermal and chemical properties werecharacterized before and after electron beam stabilization using DSC, TGA, and FT-JR. The cross-sectionalviews of resist pattern after electron beam processing were also investigated to know the chemical stability ofresist during the electron beam process. Based on the experimental results, the application possibility of electronbeam stabilization for real device fabrication below O.l4prn has been presented in this paper.Key Words : Electron Beam Stabilization, Deep-UV Photoresist, Acetal Type, Escap Type, Aspect Ratio

Photomask quality for the next generation processing such as DUV scanner lithography is critical, but there still are many problems. In this situation, we have to find some keys to solve these problems to accommodate the narrow scope of the process margin and the printing bias control on wafer, as well as coarse lithography margins. Currently, the CD uniformity of the patterned Cr, or PSM features including the repaired mask patterns, is about +/- 0.03um. In next generation photomask production, there are some fundamental difficulties to overcome as; Firstly, there is the inherent physical behavior of DUV laser on quartz substrate, and secondly, there are photomask, defects that invisible to blue laser inspection, but can still be portioned onto the wafer. In order to keep up with photomask product requirements, the next generation inspection systems are being developed with i-line and KrF laser sources. However, issues such as low-level transmission defects and critical line-widths defects have not been solved yet. In part, the Ga+ implantation defect is one of these invisible transmission defects due to the fact that the carried inspection tools use a blue laser, so it is not counted as killing defect of the DUV transmitted types. Although it is captured into a false defect, we have a difficult to classify by ion implantation defect. This paper discusses the process margins of FIB Ga+ ion scanning on the opaque repairing of damaged quartz substrate. It will show the effects of reduced intensity or using the Gas Assisted Etching process. And though it has been solved somewhat, we also have to consider the CD control specifications for the next generation device such as 1G DRAM with DUV lithography. In this experiment, we have evaluated the printability of 4X DUV scanner after both opaque and clear defect repair with a focused ion beam (FIB) system. We also confirmed the accuracy of edge repair, implantation effects of each FIB machine and determined the topography of repair by AFM.

As the design rule of devices continues to shrink, the overlay margin of layer to layer continues to become smaller. Inter-field error of overlay can be compensated by alignment parameters of the exposure system, but intra-field error of overlay is very difficult to change within a field. This paper discusses the intra-field overlay error, especially that caused by oxidation and deposition processes of a metal-oxide-silicon (MOS) integrated circuit device. In an experiment, to analyze process induced affects on the intra-field overlay error of device, we monitored thermal process, film deposition, oxidation, lithography, etching, and implantation process and pursued the trend and sources of intra-field overlay error generated in wafer process. We analyzed the affects of film stress and thermal process by measuring box and box overlay marks using the KLA metrology system at the etch process step.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Phase shift mask ( PSM ) is a useful technique to higher the resolution and focus margin in the lithography process with sub-half micron range, which is limited by currently used process tools. PSM with i-line stepper is one of the leading candidates for mass production of 64M Bit Dram. In this study, in order to obtain the information about the basic trend and process limitation of PSM, we evaluated the PSM technique by simulation and lithographic experiment. However several difficulties were encountered when attempting to use the PSM in real process. These difficulties were mainly due to the process margin and variation in munufacturing a real device. We simulated PSM by changing numerical aperture, patial coherence, focus, and pattern size for g-line and i-line. Intensity profiles of patterns were monitored for both conventional and phase shift mask ( alternating t>ye ). With those simulation results, we first analyzed the aerial image and studied the trend and limitation of PSM technology. Then we compared these results with experimental results of g-line and i-line process. Although the simulation and the experimental results showed that definable resolution limit and the resolution with depth of focus ( DOF ) margin were significantly increased by PSM technology, it was hard to control the process due to the errors occuring in manufacturing PSM. The study for resolution limit with marginal depth of focus led us to optimize the method how to approach the PSM from simulation. In addition, the process limitation and lithographic trend of PSM were investigated as well.