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The increased leakage, yield inefficiency, process, power supply, and temperature variations have significant aftereffects on the performance of complex VLSI architectures especially if mapped on ultra deep sub micrometer (UDSM) technologies. In this paper we assess the technology trend based on three industrial technologies (90, 65, and 45 nm) using a state of the art processor as benchmark: The UltraSparc Niagara 2 from SUN Microsystem. We analyze frequency, dynamic, and static power and area after synthesis varying power supply voltage and temperature. We then compare these exhaustive analyses of system level performance as a function of technology to ITRS device level estimations. The results suggest that this prediction can be of help when addressing both the technological scaling and the variability scenario of the selected technology. We believe that correctly predicting specific values on performance variations when realistic conditions and technologies are changed could provide a valuable information for the architect. Our analysis advises the designer on the effective applicability of the ITRS trends to system performance, but also pinpoints that a reliable system level prediction should better take into account the design complexity.

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm2 die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.

Dual on-chip 512-KB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13-/spl mu/m technology. Each 512-KB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 1.3 V and 85/spl deg/C. This fully integrated subsystem is composed of conventional data and tag SRAMs along with datapaths, controller, and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64-bit microprocessors, with a data latency of only four cycles including ECC correction for 128-bit data. In addition, balanced custom and automated design methodologies are used to achieve the aggressive design cycle. Architectural and physical design solutions to build this integrated short latency L2 cache are discussed.

A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two UltraSPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller, and symmetric multiprocessor bus (JBus) controllers. The 206-mm/sup 2/ die is fabricated in 0.13-/spl mu/m CMOS technology with seven layers of Cu and a low-k dielectric. The chip offers a highly efficient performance-per-watt ratio with a typical power dissipation of 23 W at 1.3 V and 1.2 GHz. A short design cycle was achieved by leveraging existing designs wherever possible and developing effective design methodologies and flows. Significant design challenges faced by this project are described. These include deep-submicron design issues, such as negative bias temperature instability (NBTI), leakage, coupling noise, intra-die process variation, and electromigration (EM). A second important design challenge was implementing a high-performance L2 cache subsystem with a short four-cycle core-to-L2 latency including ECC.

Recently, several experimental studies have been conducted on block data layout in conjunction with tiling as a data transformation technique to improve cache performance. In this paper, we analyze cache and translation look-aside buffer (TLB) performance of such alternate layouts (including block data layout and Morton layout) when used in conjunction with tiling. We derive a tight lower bound on TLB performance for standard matrix access patterns, and show that block data layout and Morton layout achieve this bound. To improve cache performance, block data layout is used in concert with tiling. Based on the cache and TLB performance analysis, we propose a data block size selection algorithm that finds a tight range for optimal block size. To validate our analysis, we conducted simulations and experiments using tiled matrix multiplication, LU decomposition, and Cholesky factorization. For matrix multiplication, simulation results using UltraSparc II parameters show that tiling and block data layout with a block size given by our block size selection algorithm, reduces up to 93 percent of TLB misses compared with other techniques. The total miss cost is reduced considerably. Experiments on several platforms show that tiling with block data layout achieves up to 50 percent performance improvement over other techniques that use conventional layouts. Morton layout is also analyzed and compared with block data layout. Experimental results show that matrix multiplication using block data layout is up to 15 percent faster than that using Morton data layout.

This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-/spl mu/m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.

A computing system's internal interconnect is a key determiner of its cost, performance, and reliability. The Sun Fireplane Interconnect, used inside the Sun Microsystems Ultrasparc III generation of servers and workstations, builds on three generations of interconnects, and provides a significant increase in performance and system bandwidth.

Process planning is an important and integral function for ensuring efficient operations in printed circuit card assembly systems. This paper presents a new approach for solving the circuit card to assembly line assignment problem to minimize assembly time. This problem occurs frequently in process planning for electronic assembly systems and involves considering other interelated process planning problems. The line assignment problem is formulated as a large-scale mixed-integer programming problem and then solved using problem decomposition along with the branch-and-bound algorithm. Techniques for improving the solution time are discussed, and the solution approach is demonstrated using industry representative data sets from Lucent Technologies. For the data sets considered, the solution approach provides solutions within 3% of optimal in approximately 6 min of computation time on a Sun UltraSparc 2 Workstation. The solution approach developed for addressing the line assignment problem can serve as a use...

We present the optimization and performance evaluation of a software-based H.263 video encoder. The objective is to maximize the encoding rate without losing the picture quality on an ordinary single processor computer such as a PC or a workstation. This requires optimization at all design and implementation phases, including algorithmic enhancements, efficient implementations of all encoding modules, and taking advantage of certain architectural features of the machine. We design efficient algorithms for DCT and fast motion estimation, and exploit various techniques to speed up the processing, including a number of compiler optimizations and removal of redundant operations. For exploiting the architectural features of the machine, we make use of low-level machine primitives such as Sun UltraSPARC's visual instruction set and Intel's multimedia extension, which accelerate the computation in a single instruction stream multiple data stream fashion. Extensive benchmarking is carried out on three platforms: a 167-MHz Sun UltraSPARC-1 workstation, a 233-MHz Pentium II PC, and a 600-MHz Pentium III PC. We examine the effect of each type of optimization for every coding mode of H.263, highlighting the tradeoffs between quality and complexity. The results also allow us to make an interesting comparison between the workstation and the PCs. The encoder yields 45.68 frames per second (frames/s) on the Pentium III PC, 18.13 frames/s on the Pentium II PC, and 12.17 frames/s on the workstation for QCIF resolution video with high perceptual quality at reasonable bit rates, which are sufficient for most of the general switched telephone networks based video telephony applications. The paper concludes by suggesting optimum coding options.

The Millstone Hill Incoherent Scatter Data Acquisition System (MIDAS) is based on an abstract model of an incoherent scatter radar. This model is implemented in a hierarchical software system, which serves to isolate hardware and low-level software implementation details from higher levels of the system. Inherent in this is the idea that implementation details can easily be changed in response to technological advances. MIDAS is an evolutionary system, and the MIDAS hardware has, in fact, evolved while the basic software model has remained unchanged. From the earliest days of MIDAS, it was realized that some functions implemented in specialized hardware might eventually be implemented by software in a general-purpose computer. MIDAS-W is the realization of this concept. The core component of MIDAS-W is a Sun Microsystems UltraSparc 10 workstation equipped with an Ultrarad 1280 PCI bus analog to digital (A/D) converter board. In the current implementation, a 2.25 MHz intermediate frequency (IF) is bandpass sampled at 1 µs intervals and these samples are multicast over a high-speed Ethernet which serves as a raw data bus. A second workstation receives the samples, converts them to filtered, decimated, complex baseband samples and computes the lag-profile matrix of the decimated samples. Overall performance is approximately ten times better than the previous MIDAS system, which utilizes a custom digital filtering module and array processor based correlator. A major advantage of MIDAS-W is its flexibility. A portable, single-workstation data acquisition system can be implemented by moving the software receiver and correlator programs to the workstation with the A/D converter. When the data samples are multicast, additional data processing systems, for example for raw data recording, can be implemented simply by adding another workstation with suitable software to the high-speed network. Testing of new data processing software is also greatly simplified, because a workstation with the new software can be added to the network without impacting the production system. MIDAS-W has been operated in parallel with the existing MIDAS-1 system to verify that incoherent scatter measurements by the two systems agree. MIDAS-W has also been used in a high-bandwidth mode to collect data on the November, 1999, Leonid meteor shower.Key words: Electromagnetics (instruments and techniques; signal processing and adaptive antennas) – Ionosphere (instruments and techniques)

Efficient scheduling of processes on processors of a Network of Workstations (NOW) is essential for good system performance. However, the design of such schedulers is challenging because of the complex interaction between several system and workload parameters. Coscheduling, though desirable, is impractical for such a loosely coupled environment. Two operations, waiting for a message and arrival of a message, can be used to take remedial actions that can guide the behavior of the system toward coscheduling using local information. We present a taxonomy of three possibilities for each of these two operations, leading to a design space of 3×3 scheduling mechanisms. This paper presents an extensive implementation and evaluation exercise in studying these mechanisms. Adhering to the philosophy that scheduling and communication are intertwined and should be studied in conjunction, a complete communication substrate for UltraSPARC workstations, connected by Myrinet and running Solaris 2.5.1, has been developed. This platform provides the entire Message Passing Interface (MPI) to readily run off-the-shelf MPI applications by employing protected low-latency user-level messaging. Several applications can concurrently use this interface. This platform has been used to design, implement, and uniformly evaluate nine scheduling strategies with a mixture of concurrent real applications with varying communication intensities. This includes five new schemes (Periodic Boost, Periodic Boost with Spin Block, Spin Yield, Periodic Boost with Spin Yield, Dynamic Coscheduling with Spin Yield) that are presented in this paper. In addition to our evaluations of the pros and cons of each mechanism in terms of throughput, response time, CPU utilization, and fairness, it is shown that Periodic Boost is a promising approach for scheduling processes on a NOW.

The UltraSPARC-III is the third generation of Sun Microsystems' most powerful microprocessors, which are at the heart of Sun's computer systems. These systems, ranging from desktop workstations to large, mission critical servers, require the highest performance that the UltraSPARC line has to offer. The newest design permits vendors the scalability to build systems consisting of 1,000+ UltraSPARC processors. Furthermore, the design ensures compatibility with all existing SPARC applications and the Solaris operating system. The UltraSPARC-III design extends Sun's SPARC Version 9 architecture, a 64-bit extension to the original 32-bit SPARC architecture that traces its roots to the Berkeley RISC-I processor. The UltraSPARC-III design target is a 600-MHz, 70-watt, 13-mm die to be built in 0.25-micron CMOS with six metal layers for signals, clocks, and power.

The accurate modeling of the nonlinear properties of materials can be computationally expensive. Parallel computing offers an attractive way for solving such problems; however, the efficient use of these systems requires the vertical integration of a number of very different software components, we explore the solution of two- and three-dimensional, small-strain plasticity problems. We consider a finite-element formulation of the problem with adaptive refinement of an unstructured mesh to accurately model plastic transition zones. We present a framework for the parallel implementation of such complex algorithms. This framework, using libraries from the SUMAA3d project, allows a user to build a parallel finite-element application without writing any parallel code. To demonstrate the effectiveness of this approach on widely varying parallel architectures, we present experimental results from an IBM SP parallel computer and an ATM-connected network of Sun UltraSparc workstations. The results detail the parallel performance of the computational phases of the application during the process while the material is incrementally loaded.

This processor uses a significant amount of integration and other techniques to enable the construction of cost-efficient SPARC computer systems that retain excellent absolute performance.

The realization of a high performance modern microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be performed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b four-way superscalar processor, but more importantly it presents the analysis and tradeoffs that were made "en route" to the final chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed.

We present a novel Physical Unclonable Function (PUF) exploiting the variability existing in a microprocessor pipeline to uniquely identify the microprocessor chip. The PUF accepts a microprocessor instruction as a challenge and produces the delay in a data path or a control path in the microprocessor as the response. The delay value is captured by over-clocking the microprocessor. The entire mechanism can be controlled by the microprocessor itself. Moreover, this PUF requires no dedicated hardware resources. It is a microprocessor-intrinsic PUF solution. We demonstrate our proposed idea using the SPARC instruction set implemented in a 32-bit LEON3 processor in a Spartan 3E FPGA. Our implementation based on the characterization of a subset of five SPARC instructions can produce 37 secure response bits for authentication.

Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.

The third generation CMT (chip multithreaded) microprocessor from Sun Microsystems has 16 cores and is optimized for high throughput without compromising high single thread performance. This paper describes the unique challenges faced in DFX of this complex CMT processor and the DFX solutions deployed. Some of the notable new DFX features include a highly configurable scan architecture, a memory test network that leverages functional access paths, BIST of special memories, and a test mode for running functional tests in the presence of non-deterministic serdes interfaces. Identification of chips with partially good cores and caches is supported in manufacturing for yield and in the field for availability.

Processor architecture is undergoing a significant change in response to the rapidly escalating complexities of high-power, high-frequency, and increasingly superscalar designs. Evolutionary multi-core and aggressively multi-threaded chips are appearing in the general purpose microprocessor space. The latter offer simplicity, low power, and high performance on threaded workloads but with somewhat reduced single thread performance. This paper examines the performance of the SPARC64(TM) VI, a dual-core 4-thread processor, and the UltraSPARC(TM) T1, an 8-core 32-thread processor. Numerous workloads are executed on both designs. These include single thread speed tests, homogeneous throughput tests, and multi-threaded tests using varying amounts of data and parallelism. The results indicate a clear separation in the workloads that are best suited to each design. To reap the full benefit of these multi-threaded designs, software has to be architected to use as many threads as possible. This shift is likely to affect both software developers and compiler writers for the next several years.

This paper presents the testing methodology of the UltraSPARC T1 microprocessor and the challenges to productizing the industry's first 8 cores and 32 thread microprocessor. The challenges include effectively testing 8 individual cores that share common functional blocks (L2 cache, cache crossbar, floating point unit), reducing 8times conventional production test time and tester memory while achieving the same coverage, and productizing 6 core or 8 core devices at the targeted frequency. Highlights of DFT features designed to overcome the challenges are presented followed by a production flow together with key learning and future improvement plans

As the complexity of microprocessors increases, the design and bring-up times have significantly increased, negatively impacting the time-to-market (TTM) requirements. In this paper, a backtracing methodology for identifying the root cause of functional failures on the UltraSPARCtrade family of processors is presented. Data provided by a scan dump analysis methodology is linked not only to the design database but also to the failing test in order to isolate one or several candidates for further analysis

This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 and SGI Altix 3700. The OSCAR compiler hierarchically exploits the coarse grain task parallelism among loops, subroutines and basic blocks and the near fine grain parallelism among statements inside a basic block in addition to the loop parallelism. Also, it allows us global cache optimization over different loops, or coarse grain tasks, based on data localization technique with inter-array padding to reduce memory access overhead. Current performance of OSCAR compiler is evaluated on the above SMP servers. For example, the OSCAR compiler generating OpenMP parallelized programs from ordinary sequential Fortran programs gives us 5.7 times speedup, in the average of seven programs, such as SPEC CFP95 tomcatv, swim, su2cor, hydro2d, mgrid, applu and turb3d, compared with IBM XL Fortran compiler 8.1 on IBM pSeries 690 24 processors SMP server. Also, it gives us 2.6 times speedup compare with Intel Fortran Itanium Compiler 7.1 on SGI Altix 3700 Itanium 2 16 processors server, 1.7 times speedup compared with NEC Fortran Itanium Compiler 3.4 on NEC TX7/i6010 Itanium 2 8 processors server, 2.5 times speedup compared with Sun Forte 7.0 on Sun Ultra 80 UltraSPARC II 4 processors desktop workstation, and 2.1 times speedup compare with Sun Forte compiler 7.1 on Sun Fire V880 UltraSPARC III Cu 8 processors server.

A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.

Some new mathematical algorithms related to spacecraft thruster selection problems have been designed, implemented, and tested. The proposed approach is based on the concept of precomputing a set of optimal combinations of thrusters and storing the according data in the onboard computer (OBC) memory. During the nominal flight of a spacecraft, only a look-up procedure will be required to select, in the real-time mode, the right combination of not more than six thrusters (for a six-dimensional task) and their firing times. For off-nominal situations, when the spacecraft propulsion subsystem has to often operate at the edge of its capability and provide maximum linear and/or angular control accelerations, an additional algorithm has been proposed based on a modification of the parametric simplex method, Real-time software implementing the proposed algorithms requires from 0.05 ms to 0.21 ms to be executed on a SUN workstation with a 550-MHz UltraSparc processor. Regarding the size of OBC memory required for storing real-time computation data, only 52 KB are needed for a spacecraft with 20 thrusters. The user is provided with the flexibility to select the option, which better meets specific criteria and constraints such as execution time and accuracy of the optimal solution (at the expense of execution time or memory). In addition to C-code implementation, the software module (intended for real time) could be implemented as a standard SIMULINK library block and can be integrated with different simulators for test purposes. The software implemented in the project demonstrated effectiveness and robustness of the designed algorithms both in open-and closed-loop tests including various spacecraft maneuvers.

A processor core, previously implemented in a 0.25 μm AI process, is redesigned for a 0.13 μ m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed.

Transistors fabricated with thin gate-oxides are vulnerable to dielectric damage and reliability problems due to excessive electric field. Recently, the difference between operating voltage and maximum allowed gate-source voltage (Vgs) and gate-drain voltage (Vgd) of MOS transistors has decreased significantly. This presents special challenges for I/O designers, since transistors used in I/O buffers are subjected to higher Vgs/Vgd than those used in the core because of switching noise, signal reflections, and ground bounce. The problem is worse in chip redesign projects due to layout area, supply and methodology constraints. In this application, the microprocessor redesign is targeted to 1.9V technology in 0.21/spl mu/m process which imposes the constraint of 2.2V and 1.9V as the maximum transient and DC limits.

The SuperSPARC microprocessor is a highly integrated, high-performance superscalar SPARC version 8 compatible microprocessor. The authors provide an overview of its internal operation and capabilities. The processor contains an integer unit, a double precision floating point unit, fully consistent instruction and data caches, a SPARC reference memory management unit and a dual-mode bus interface supporting either the SPARC standard MBUS or an interface optimized for connection to a companion second-level cache controller chip. The chip is constructed using Texas Instruments 0.8- mu triple-layer metal BiCMOS technology. >

UltraSPARC-I is the first microprocessor from Sun Microsystems to implement the new 64-bit SPARC V9 architecture. UltraSPARC-I is a superscalar processor capable of issuing up to four instructions together and possesses several features designed to enable high performance on a variety of applications. While UltraSPARC-I maintains strict binary compatibility with and delivers excellent performance on thousands of existing 32-bit applications developed for other SPARC processors, even more benefit can be derived by using a compiler that specifically targets it. This paper discusses various features of UltraSPARC-I and the compiler techniques used to leverage them to obtain high performance on many floating point programs.

Successful manufacturing ramp of a complex high speed microprocessor requires quick and reliable test and diagnostic methods. Some commonly used debug techniques for the UltraSPARC family of devices are presented with actual result of some diagnosed failures.

SCI is based on unidirectional point-to-point links connected in rings. Separate rings can be connected using switches to allow for larger configurations than are feasible with a single ring. The SCI standard is implemented in the LinkController (LC-1) chip from Dolphin Interconnect Solutions. Experiments are conducted on a set of Sun UltraSparc workstations connected by the new Sbus/SCI adapters based on the LC-1. The practical limit on the number of nodes on a ring depends on the host interface and the link capacity and tuning, as well as the expected interconnect load. Single ring configurations of up to 10 nodes on a ring and 4 and 8 node systems using multiple smaller rings connected through a 4-way switch are analysed with respect to latency and network throughput. Results demonstrate a peak aggregate ring bandwidth of 187 Mbytes/s in a 10 node ring configuration, and a peak bandwidth of 153 Mbytes/s for the 4-way switched 8 node system. Results also show that the interconnect is sensitive to certain traffic patterns, and that different topologies have different weak spots in this sense.

The overall verification approach used in the design and development of the full custom 64 bit UltraSPARC microprocessor is described. A balanced hierarchical approach is critical in validating a design with this level of complexity. The tools, developed internally and externally, which aided the verification effort are also described. The environment is flexible enough to support various revisions of major tools. The method developed could easily be applied to derivative and next generation microprocessors.

This paper describes the testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor. Due to the aggressive nature of this high performance design, these three areas needed to be addressed at the beginning of the project to ensure success. We present the goals and analysis that lead to our decisions as well as the actual features that were implemented. The features described in this paper have helped enormously in achieving the time-to-volume goals and hence the overall success of the product.

The design, implementation, and verification of the power distribution network for the 5.2 million transistor UltraSPARC-I microprocessor is described. A novel simulation method allows rapid identification of exact layout locations with potential electromigration or excessive voltage drop problems. Hierarchical verification capabilities of this approach are utilized to design an efficient and robust distribution of V/sub dd/ and V/sub ss/ across a large die, in the face of stringent IR drop and floorplanning constraints. A comprehensive methodology for power distribution and management, along with seamless integration of the power distribution into existing CAD tools throughout the design cycle results in correct-by-construction power networks for cell libraries and functional blocks, area efficient power interconnections and reduced time-to-market due to correction of all reliability failures in the power networks prior to mask generation.

UltraSPARC is the first microprocessor from Sun Microsystems' SPARC Technology Business to implement the new 64-bit SPARC V9 architecture. ULtraSPARC is equipped with unique multimedia capabilities and is capable of 4-way superscalar instruction dispatch, with an emphasis on maximal system efficiency and throughput in the execution of complex, memory-intensive applications. UltraSPARC maintains a strict binary compatibility with the thousands of existing 32-bit applications developed for other SPARC processors. This paper describes the feature set and operation of UItraSPARC.

This paper describes the visual instruction set (VIS). This is a RISC-like extension to the SPARC V9 instruction set that provides core instructions that greatly enhance the graphics and image processing capabilities of SPARC processors. VIS's first implementation is in the new UltraSPARC microprocessor.

Sun has a diverse workstation and server product line suitable for high performance technical computing. In this talk we will present an overview of the architectural features of UltraSPARC(tm) processor based product families. The product families are built around three series of UltraSPARC processors, namely, S, I and E series. The S series processors (UltraSPARC I, II and III) are designed for highest performance. These are used in high end workstations and low, mid and high range server class systems. The I series processors (UltraSPARC IIi) are optimized for price/performance ratio. This has been achieved by a high level of system integration. The E series processors (UltraSPARC IIe) are targeted towards embedded applications and optimized to minimize energy consumption requirements. Supporting the processor implementations is a family of memory interconnects. We will describe the design characteristics of the Ultra Port Architecture(tm), Gigaplane(tm), Gigaplane XB(tm) and the Sun Fireplane(tm) system interconnects, respectively. Representative results of benchmarks such as SPEC CPU2000, Imbench and STREAM will be presented for various systems and discussed in the context of scalable parallel computing applications.

The IEEE Std 1149.1 features have been essential in system and chip debug, test and manufacturing of UltraSPARC-III product. Several key testability features were achieved by adding a suite of customized instructions and logic to the chip core and I/Os to allow test and debug when in test mode or debug during normal operations. In addition, due to the design of high speed I/Os, extra logic was added to Boundary-Scan to maintain compliancy and provide support for all test and debug features. This paper discusses the above features and their logic implementations.

UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.

This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment. Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team. The team adopted a combination of standard, "classic" techniques and methodologies, as well as some new innovative approaches. This mixture of old and new led to a well-balanced, robust verification flow which enabled finding the majority of the design problems (bugs) early in the pre-silicon stage of the project. This paper discusses an internal tool (Sniper) (patent pending) which increases the processor bus activity in a way which would uncover subtle coherency problems.

Most advanced forms of security for electronic transactions rely on the public-key cryptosystems developed by Rivest, Shamir and Adleman. Unfortunately, these systems are only secure while it remains difficult to factor large integers. The fastest published algorithms for factoring large numbers have a common sieving step. These sieves collect numbers that are completely factored by a set of prime numbers that are known in advance. Furthermore, the time required to execute these sieves currently dominates the runtime of the factoring algorithms. We show how the sieving process can be mapped to the Mojave configurable computing architecture. The mapping exploits unique properties of the sieving algorithms to fully utilize the bandwidth of a multiple bank interleaved memory system. The sieve has been mapped to a single programmable hardware unit on the Mojave computer, and achieves a clock frequency of 16 MHz. The full system implementation sieves over 28 times faster than an UltraSPARC Workstation. A simple upgrade to 8ns SRAMs will result in a speedup factor of 160.

The goal of the NOW project was to explore and demonstrate a fundamental change in approach to the design and construction of large scale computing systems. This was motivated by the desire to deploy powerful systems very rapidly and to scale them incrementally, as is required to fully utilize commercial technologies that are advancing at a high rate, to meet new service demands that are increasing on internet time, and to address emergency or military situations. The key enabling technology for the project was the emergence of scalable, low latency, high bandwidth VLSI switches, pioneered in massively parallel processors and transferred into system area network (SAN) configurations. With SAN technology, it became feasible to construct powerful, integrated systems by literally plugging together many state of the art commercial workstations or PCs to form a high performance cluster. The project demonstrated the design approach, the solution to core challenges, and novel design opportunities by building and utilizing a cluster of over one hundred Ultrasparc workstations interconnected by a multigigabyte Myricom network.

Efficient scheduling of processes on processors of a Network of Workstations (NOW) is essential for good system performance. However, the design of such schedulers is challenging because of the complex interaction between several system and workload parameters. Coscheduling, though desirable, is impractical for such a loosely coupled environment. Two operations, waiting for a message and arrival of a message, can be used to take remedial actions that can guide the behavior of the system towards coscheduling using local information. We present a taxonomy of three possibilities for each of these two operations, leading to a design space of scheduling mechanisms. This paper presents an extensive implementation and evaluation exercise in studying these mechanisms. Adhering to the philosophy that scheduling and communication are intertwined and should be studied in conjunction, a complete communication substrate for UltraSPARC workstations, connected by Myrinet and running Solaris 2.5.1, has been developed. This platform provides the entire Message Passing Interface (MPI) to readily run off-the-shelf MPI applications by employing protected low-latency user-level messaging. Several applications can concurrently use this interface. This platform has been used to design, implement, and uniformly evaluate nine scheduling strategies with a mixture of concurrent real applications with varying communication intensities. This includes four new schemes (Periodic Boost, Periodic Boost with Spin Block, Spin Yield, Periodic Boost with Spin Yield) that are presented in this paper. In addition to evaluatThis research is supported in part by an NSF Career Award MIPS-9701475, NSF grant MIP-9634197 and an NSF equipment grant CDA-9617315. ing the pros and cons of each mechanism in terms of throughput, response time, CPU utilization and fairness, it is shown that Periodic Boost is a promising approach for scheduling processes on a NOW.

The demand for high-speed FPGA compilation tools has occured for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing has grown more dramatically than the compute power of the available computers. Second, there exists a subset of users who are willing to accept a reduction in the quality of result in exchange for a high-speed compilation. Third, high-speed compile has been a long-standing desire of users of FPGA-based custom computing machines, since their compile time requirements are ideally closer to those of regular computers. This paper focuses on the placement phase of the compile process, and presents an ultra-fast placement algorithm targeted to FPGAs. The algorithm is based on a combination of multiple-level, bottom-up clustering and hierarchical simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time. For example, it can generate a placement for a 100,000-gate circuit in 10 seconds on a 300 MHz Sun UltraSPARC workstation that is only 33% worse than a high-quality placement that takes 524 seconds using a pure simulated annealing implementation. In addition, operating in its fastest mode, this tool can provide an accurate estimate of the wirelength achievable with good quality placement. This can be used, in conjunction with a routing predictor, to very quickly determine the routability of a given circuit on a given FPGA device.

This paper gives an overview of the VGDS (Virtual Global Data Structure) project. The VGDS e ort focuses on developing an integrated, distributed environment that allows fast prototyping of a diverse set of simulation problems in scienti c and engineering domains, including regular, irregular, and adaptive problems. The framework de nes three base libraries, Array, Graph, and Tree, that capture major data structures involved in scienti c computation. The framework de nes multiple layers of class libraries which work together to provide data-parallel representations to application developers while encapsulate parallel implementation details into lower layers of the framework. The layered approach enables easy extension of the base libraries to a variety of application-speci c data structures. Experimental results on a Sun UltraSparc workstation cluster is reported.

SCI is based on unidirectional point-to-point links forming ringlets that can be connected with switches to allow further scaling. This paper presents performance results from running on a number of differently configured SCI clusters. The SCI technology used is Dolphin's second generation PCI/SCI adapter based on the LC-2 LinkController chip as well as a new 4 port, LC-2 based switch. Nodes are UltraSparcs running Solaris 2.5.1 as the operating system. Results show latencies down to 2.9 Μsec for remote stores, and bandwidths up to 80 Mbytes/s into a single system. Network throughput of more than 270 Mbytes/s (8 node system) is demonstrated. Results indicate that the new LC-2 eliminates a number of problems with the earlier LC-1 chip in addition to increasing peak performance. With its flexible building blocks this technology should also make it possible to construct systems with a large number of nodes, pushing I/O adapter based SCI interconnects forward as a promising system area network technology.

The Starfire Ultra Enterprise 10000 extends the envelope of UNIX SMP systems in several dimensions. Interconnect: It uses four address routers and a 16x16 data crossbar to provide 64 UltraSPARC processors with uniform-memory access at a bandwidth of 10,667 MBps. Flexibility: Starfire can be dynamically reconfigured into multiple hardware-protected operating system domains. Robustness: specially-connected workstation orchestrates service activities. Failing boards can be hot-swapped without interrupting system operation. ECC is carried on both address and data paths. Performance: Starfire has set several TPC-D decision- support benchmark records. It delivers a respectable 21 Gflops on Linpack-parallel.

Seismic wave modelling algorithms used for calculating the seismic response of a given earth model, require large computational resources in terms of speed and memory. In this paper we describe the PVM (Parallel Virtual Machine) implementation of these algorithms in a distributed computing environment. Both the acoustic and elastic wave modelling equations are formulated as a first order hyperbolic system. Numerical solution uses an explicit finite difference scheme, which is fourth order accurate in space and second order accurate in time. A domain decomposition algorithm is used for distributing the workload and the tasks communicate via PVM message passing calls. The efficiency and speed of the algorithms is tested on a cluster . of SUN UltraSparc workstations.

The 5.2 M transistor UltraSPARC(TM)-I microprocessor is manufactured using the 0.5 micrometer EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.

Rapidly changing demands in the microprocessor industry require that new products be quickly brought to volume production on the fastest fabrication process available. Two key metrics of success for manufacturing start-up of a microprocessor are manufacturing yield and product performance. We have developed a comprehensive data collection and analysis system to speed identification, measurement, diagnosis and resolution of yield and performance bottlenecks and therefore accelerate yield and performance improvement of the UltraSPARC-I microprocessor. Our system is based on automated collection of wafer processing and electrical parametric data plus detailed defect map, test and performance data collected for every microprocessor manufactured. This system and its application to yield and performance improvement are presented in this paper.

The UltraSPARC-I microprocessor is tested at several stages in the manufacturing flow to screen out any chips which contain manufacturing defects and to sort chips by speed. Custom test hardware and software have been developed to perform production test of UltraSPARC-I in both wafer and packaged form. To speed up chip yield and performance improvement, we collect detailed yield and performance measurement data during test of every microprocessor manufactured. The data collected includes detailed pass or fail results of individual patterns, performance measurements of maximum operating frequency and Vcc, parametric measurements of transistor saturation currents and ring oscillator frequencies, and Idd measurements. The goal of our data collection is to provide, without the need for engineering retest, immediate diagnostic information on why each chip yielded and performed as it did, enabling yield and performance issues to be quickly identified and subsequently resolved.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.