Search

Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors (QPDs) or active pixel sensor (APS). These devices are intended to measure slight movements of laser spots. The QPD are, by far, the best approach in terms of resolution and noise, but requires complex and expensive x - y micropositioners to perform sensor alignment with the incoming laser spot. The APSs are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrisic digital nature, the SNR and the resolutions are degraded in APS. In this paper, a new type of device called configurable QPD and its theory of operation is presented. This new device combines the analog operation of the QPD with the configurability of the APS, by means of combining photodetectors elements with analog switches in a matrix-shaped architecture. Finally, a prototype chip has been fabricated and tested and its measurements results are presented.

Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors and active pixel sensors. These devices are intended to measure slight movements of a laser spot. Quadrant photodetectors (QD) are, by far, the best approach in terms of resolution and noise, but require complex and expensive micropositioning machinery to perform sensor alignment with the incoming laser spot. Active pixel sensors (APS) are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrinsic digital nature, the SNR and resolutions are degraded in APS. In this article, a new type of device called configurable quadrant photodetector (CQD) is presented. It combines the analog operation of the QD with the configurability of the APS, by means of combining photodetector elements with analog switches in a matrix-shaped architecture. A prototype has been designed, fabricated, and tested, and its electrical characterisation is presented.

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

Classification of Internet protocol (IP) packets has become a bottleneck for the effective operation of QoS capable routers. In this paper, a novel packet classification scheme for high performance routers on different QoS architectures, named split-engine packet classification (SPC), is proposed. The key feature of the presented architecture is its ability to address a wide variety of inherently incompatible performance requirements by efficiently combining existing classification methods. To prove the validity of the proposed approach, a low cost SPC packet classifier architecture with per-flow packet treatment and dynamic resource reservation support on an OC-24 link as required by the Integrated Services framework, has been developed.

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.