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The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.

The stress related shifts of transistors are measured by precise stress application with a newly designed in-situ four-point bending (4PB) system. A test board including a flip chip packaged test vehicle is loaded with uniaxial stress. The test vehicle contains dedicated ring oscillator circuits fabricated in the 22 nm FDSOI technology node, used to evaluate the effects of thermo-mechanical stress on the characteristics of CMOS devices. Finite element simulation provides insight into the originated stress values in the board, package, and active devices during mechanical loading. Considering the bending caused stress in the devices and the specific layout of the circuits, the directional frequency shifts of the circuits under stress are derived. These shifts are compared with a previous indentation study, which has been developed to induce very localized loads. The comparison aims for verification of the indentation approach to study directional stress related effects as well as very localized effects in chip stacks.

The stress-related change in the characteristics of transistors manufactured in the 22 nm fully depleted silicon on insulator (FDSOI) CMOS technology node is studied with advanced experimental indentation setups. Precisely, NAND and NOR ring oscillator circuits are used to monitor the strain-caused mobility deviations in the silicon transistor channels. Piezoresistive coefficients for strained silicon are calculated from the experimental indentations data using spherical and cylindrical tip geometries. In contrast to spherical tips, the cylindrical indentation tips enable to induce the stress more selectively into a desired direction. To set up the experimental details appropriately, finite element (FE) simulations have been used. Additionally, FE method (FEM) studies are conducted to compute the quantitative strain values in the silicon transistor channels as a function of contact load as well as chip and tip geometries. Using the signal deviations of the RO circuits subjected to strain from spherical and cylindrical indentation, a set of equations using the linearized piezoresistive model are created to determine the directional piezoresistive coefficients.

The impact of strain, induced by nanoindentation, on integrated circuit performance is measured. Localized strain caused by chip- package interaction alters the charge carrier mobility in the transistor channel due to the piezoresistive effect. Instrumented indentation enables to induce controlled localized loads with high lateral precision, and it is used to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in 22 nm FDSOI technology are used as a sensor to monitor the strain effect on transistor performance. Novel tip geometries provide insight into the direction dependent strain impact. Strain/stress fields at transistor level are determined by complementary FEM simulation. Board bending experiments with uniaxial stress/strain conditions are performed to verify the approach. The established correlation of mechanical load and device performance is used to provide an estimate for the effect of package related stress on transistor performance.

Chip-package interaction-caused mobility degradation in CMOS transistors is a critical degradation mechanism for microelectronic devices. An approach based on nondestructive indentation is applied to induce highly localized stress fields. Strain-sensitive ring oscillator circuits are integrated to monitor parametric deviations during mechanical loading. In this study, the indentation technique is used to investigate the impact of the chip layout and geometry of a flip chip-packaged test chip. Complementary FE simulation provides a better understanding of the relevant stress-strain fields and enables a comparison of the parametric circuit deviations within a dedicated stress tensor. The results demonstrate the capability to study the stress-strain distribution in microelectronic devices during external loading with indentation and to determine its impact on transistor degradation.