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A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yields 5.7 dB of MSG at 150 GHz. Measurement shows the amplifier exhibits 8.2 dB of gain, 6.3 dBm of Psat, 1.5 dBm of PidB and 27 GHz of 3 dB bandwidth, while consuming 25.5 mW at 1.1 V. The dummy-prefilled microstrip line exhibits QTL ? 12 up to 200 GHz.

Peak f T of 660GHz is reported for HBT f T doubler designs in IBM 90nm SiGe BiCMOS technology 9HP. This high performance f T doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and f T is also investigated. f T doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

High performance Schottky Barrier Diodes (SBDs) with cut-off frequency (fc) ~2.0 THz integrated into a 90nm SiGe BiCMOS technology for millimeter wave (mm-wave) applications are presented in this paper. To our knowledge, this is the highest reported fc for a SBD in a BiCMOS technology. The SBDs reported here have low reverse bias leakage with breakdown voltage of ~5V, and have been integrated in the base technology without the addition of any extra processing step. The affects of variation of critical process and device parameters - undoped silicon layer (n-epi) thickness, thermal cycle associated with deep-trench formation, cathode reach-through width, and anode area on device performance have also been investigated and are presented here.

Having two, or more, transistors with different values of f T and BV CEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricating these transistors on the same wafer is another important factor. Three different approaches for co-integrating high-performance and high-breakdown SiGe npn HBTs with minimal process deviation are presented herein. The work features a high-performance HBT with f T × BV CEO product of 500GHz-V and a high-breakdown HBT with over 430GHz-V integrated on the same wafer with one-mask deviation.

Mm-wave digitally-controlled oscillators (DCOs) with reconfigurable passive resonators are proposed, which achieve wide tuning range (>10%) and fine frequency resolution (9.7% linear tuning range and phase noise lower than −90.5 dBc/Hz at 1-MHz offset across the 56–62 GHz range. The T-DCO achieves fine frequency tuning step of 2.5 MHz, whereas that of the L-DCO is better than 160 kHz. The L-DCO and T-DCO consume 10 mA and 12 mA, respectively, from a 1.2-V supply. The core size of each DCO is 0.4×0.4 mm2.

A millimeter wave (MMW) on-chip passive frequency-dependent inductor is described with different designed inductance values targeted at different frequency ranges using one device. The proposed frequency-dependent inductor design allows the optimization of multi-band impedance matching for MMW analog circuit designs with a single all-passive on-chip device. This device uses low-loss natural capacitors and multiple capacitively loaded ground return lines to provide MMW frequency-dependent effective device inductance. No on-chip switches are required in the proposed inductor design and it can allow circuit size reduction by allowing a single inductor to target different frequency ranges. Simulated inductance values in a 130 nm BiCMOS technology show a 61% change in inductance is possible between two frequency ranges: f 48 GHz. The proposed frequency-dependent inductor design has also been designed and measured in a 45 nm CMOS process. Measured results show that the use of multiple capacitively loaded ground return lines is effective in creating an on-chip MMW frequency-dependent inductor.

Sub-1V supplies limit the output voltage swing and saturated output power of an amplifier integrated in deep-submicron CMOS technology. Aside from absolute output power, power-added efficiency (PAE), stability and gain are also important power-amplifier (PA) design considerations. High reverse isolation between output and input is necessary to mitigate the effects of antenna mismatch, limit unwanted interference between circuit blocks on-chip and to promote stability. Efficiency of the PA is also paramount for portable consumer electronic applications operating from a battery, such as short-range Gb/s communication SoCs operating in the unlicensed bands around 60GHz. Aside from the 60GHz band, long-range collision-avoidance radar for automobiles (77/79GHz), and radio imaging (94GHz) are also potential applications for CMOS at mm-wave frequencies [1–4].

Radio applications beyond 100GHz that will benefit from silicon technologies [1–5] include high-rate communication links, medical imaging systems, and chemical sensors. Challenges in CMOS mm-wave front-ends include low available transistor gain and strict metal density rules which alter passive element characteristics [1, 2, 5, 6].

This paper presents an LC-tuned, 24-GHz single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in 90-nm CMOS. The design focuses on the techniques to increase the power handling capability in the transmit (Tx) mode under 1.2-V operation. The switch achieves a measured P-1dB of 28.7 dBm, which represents the highest linearity, reported to date, for CMOS millimeter-wave T/R switches. The transmit and receive (Rx) branches employ different switch topologies to minimize the power leakage into the Rx path during Tx mode, and hence improve the linearity. To accommodate large signal swing, AC floating bias is applied using large bias resistors to all terminals of the switch devices. Triple-well devices are utilized to effectively float the substrate terminals. The switch uses a single 1.2-V digital control signal for T/R mode selection and for source/drain bias. The measured insertion loss is 3.5 dB and return loss is better than -10 dB at 24 GHz.

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fT's of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

We present results of an interlaboratory comparison of S-parameter and noise-parameter measurements performed on 0.12 µm gate-length CMOS transistors. Copies of the same device were measured at three different laboratories (IBM, NIST, RFMD), and the results were compared. Each of the laboratories used a different measurement method, although two used similar commercial systems. Effects of different calibration reference planes are shown. The devices measured have large values of |S 11 |, |S 22 |, and |Γ opt |, and have very low minimum noise figures (below 0.2 dB) over some of the frequency range. For the most part, the measurements at the different laboratories are in reasonable agreement, though there are discrepancies. It is also evident that the noise performance of the devices is better than our ability to measure it.

This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.

DC and RF characteristics of Si nFETs and SiGe HBTs are compared in IBM's leading-edge production RFCMOS and BiCMOS technologies at 90 and 130 nm nodes respectively. Underlying performance trade-offs to achieve low power circuit operation are investigated.

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

A force‐based scanning Kelvin probe microscope has been used to image dopant profiles in silicon for integrated circuit devices on a submicron scale. By measuring the potential difference which minimizes the electrostatic force between a probe and surface of a sample, an estimate of the work function difference between the probe and surface may be made. To the extent that this work function difference is a consequence of the dopant concentration near the sample surface, doping profiles are inferred from the measurements. An overview of the measurement technique is presented, along with several examples of resulting dopant imaging of integrated circuits.