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The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, nand, and nor gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits.

Overcoming the drawbacks of the existing ferroelectric tunnel junction (FTJ) models which ignore the dynamic or multi-domain switching behaviors, we develop a more comprehensive FTJ model by combining the Time-Dependent Landau-Ginzburg (TDLG) equations to solve the multi-domain dynamic switching of ferroelectric layer and the Non-Equilibrium Green Function (NEGF) to solve the tunneling current. The model successfully reproduces the experimental results of our fabricated metal-ferroelectrics-insulator-semiconductor (MFIS) FTJ. This model empowers us to predict both the dynamic and multi-state switching of FTJ, showing its promise for applications in the high-density data storage and analog computing.

We report the temperature-dependent operation of back-end-of-line (BEOL) compatible amorphous indium-gallium-zinc-oxide ( ${a}$ -IGZO) ferroelectric thin-film transistors (FeTFTs) with a large memory window (MW) more than 3 V. Our ${a}$ -IGZO FeTFTs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stru- cture with Zr-doped HfO 2 (HZO) as the ferroelectric layer. Characteristics of ${a}$ -IGZO FeTFTs are investigated in the temperature range of −40 °C to 100 °C. We found that: Firstly, the remanent polarization ( ${P}_{\text {r}}$ ) of the HZO film increases with $2{P}_{\text {r}}$ from $\sim 35~ {\mu }\text{C}$ /cm 2 at −40 °C to $\sim 40~ {\mu }\text{C}$ /cm 2 at 100 °C. Secondly, enhancement in MWs at high temperatures is observed, achieving MWs larger than 3.5 V when the temperature is higher than 60 °C. Thirdly, for the threshold voltage ( ${V}_{\text {TH}}$ ) at high temperatures, there is a competition between the negative shift caused by higher carrier concentration in the ${a}$ -IGZO channel and positive shift due to the charge trapping at the floating gate in the MFMIS structure. This could be explored to realize good ${V}_{\text {TH}}$ stability.

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors (α -IGZO NW-FETs) featuring an ultrascaled nanowire width ( $W_{NW}$ ) down to ~20 nm. The device with 100 nm channel length ( $L_{CH}$ ) and ~25 nm $W_{NW}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance ( $G_{m,ext}$ ) of 612 μ S/μ m at a drain-source voltage ( $V_{DS}$ ) = 2 V (456 μ S/μ m at $V_{DS}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high-k HfO₂ as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl₃-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of $W_{NW}$ improves the SS notably without sacrificing on-state performance, and the shrinking of $L_{CH}$ boosts the $G_{m,ext}$ . The ultrascaled α -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired.

In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ( $\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing ( SS ) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage ( ${V}_{\text {TH}}$ ), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V.

A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over $1\times 10^{21}$ cm−3 in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.

In this letter, we proposed and experimentally demonstrated a metal-insulator-semiconductor (MIS) ferroelectric capacitor with non-volatile programmable capacitance. By switching the polarization of the Al-doped HfO2 ferroelectric insulator with the external electric field, the depletion width of the semiconductor can be modulated, leading to the continuously adjustable capacitance of the device. Due to the non-volatility of ferroelectricity, the programmed capacitance is stable without the constant DC bias. We also proposed some potential applications of the capacitor in the data storage and circuit design.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

For the first time, this study experimentally validates that the depolarization field ( ${E}_{\text {DE}}$ ) in the ferroelectric (FE) film leads to voltage gains in negative capacitance (NC) field-effect transistors (FETs). For both NCFETs with and without a floating gate, the steeper subthreshold swing (SS) and the enhanced ${I}_{\text {ON}}$ are achieved under dc and pulse measurements corresponding to the measured voltage gains ( dV int/ dV GS > 1). Furthermore, the voltage gains are theoretically calculated based on the depolarization theory and the voltage distribution across the gate-stack, showing good agreements with the measured results. In conclusion, ${E}_{\text {DE}}$ in an FE film produces the NC effect and the voltage gains. Even with ${P} /cm2, sufficient ${E}_{\text {DE}}$ is still produced in NCFETs to achieve improved electrical performance over the reference MOSFET. These findings suggest a way for low-voltage and high-reliability NCFETs.

Here we report the ZrOx-based negative capacitance (NC) FETs with 45.06 mV/decade subthreshold swing (SS) under ± 1 V VGS range, which can achieve new opportunities in future voltage-scalable NCFET applications. The ferroelectric-like behavior of the Ge/ZrOx/TaN capacitors is proposed to be originated from the oxygen vacancy dipoles. The NC effect of the amorphous HfO2 and ZrOx films devices can be proved by the sudden drop of gate leakage, the negative differential resistance (NDR) phenomenon, the enhancement of IDS and sub-60 subthreshold swing. 5 nm ZrOx-based NCFETs achieve a clockwise hysteresis of 0.24 V, lower than 60 mV/decade SS and an 12% IDS enhancement compared to the control device without ZrOx. The suppressed NC effect of Al2O3/HfO2 NCFET compared with ZrOx NCFET is related to the partial switching of oxygen vacancy dipoles in the forward sweeping due to negative interfacial dipoles at the Al2O3/HfO2 interface.

We fabricated and investigated the electrical characteristics of Ge pFinFET on (100)-oriented GeOI wafer. Transistors with fin channel along [110] direction demonstrate the improved drive current and channel ΔRtot/ΔLG compared to the devices along [100] direction. At a Qinv of 5 × 1012 cm−2, GeOI FinFETs along [110] direction have 60% and 10% improved μeff in comparison with [100] devices and Si university mobility, respectively.

Ferroelectric field effect transistor (FeFET) emerges as an intriguing non-volatile memory technology due to its promising operating speed and endurance. However, flipping the polarization requires a high voltage compared with that of reading, impinging the power consumption of writing a cell. Here, we report a CMOS compatible FeFET cell with low operating voltage. We engineer the ferroelectric Hf1-xZrxO2 (HZO) thin film to form negative capacitance (NC) gate dielectrics, which generates a counterclock hysteresis loop of polarization domain in the few-layered molybdenum disulfide (MoS2) FeFET. The unstabilized negative capacitor inherently supports subthermionic swing rate and thus enables switching the ferroelectric polarization with the hysteresis window much less than half of the operating voltage. The FeFET shows a high on/off current ratio of more than 107 and a counterclockwise memory window (MW) of 0.1 V at a miminum program (P)/erase (E) voltage of 3 V. Robust endurance (103 cycles) and retention (104 s) properties are also demonstrated. Our results demonstrate that the HZO/MoS2 ferroelectric memory transistor can achieve new opportunities in size- and voltage-scalable non-volatile memory applications.

In this letter, we experimentally investigate the impact of polarization ( ${P}$ ) switching behaviors on hysteretic and near hysteresis-free (NHF) negative capacitance field-effect transistors (NCFETs). Compared with the typical abrupt ${P}$ switching in hysteretic devices, NHF NCFETs show gradual and continuous response of ${P}$ under applied voltage, indicating that the mechanism underlying NHF characteristics is incomplete dipoles flipping, rather than complete dipoles switching. It has also been confirmed by a small amount of ${P}$ charge ( $0.1\sim 0.2 {\mu }\text{C}$ /cm2), which is still capable of achieving electrical performance improvement. This favors the device operation voltage scaling and reliability improvement for logic transistor applications.

We demonstrate negative capacitance (NC) Ge field-effect transistors (FETs) utilizing the TaN/HfZrO x /SiO2 gate stack. Typical characteristics of NC transistors, including the sub-60 mV/decade subthreshold swing (SS), the gate capacitance ${C} _{G}$ peak, and the negative differential resistance effect are achieved in NC Ge FETs without internal metal gate. Significant ${C} _{\textit {G}}$ peak, as the evidence of NC effect is obtained in NC transistors at the frequency up to MHz. Ferroelectric Ge FETs with counterclockwise ${I} _{\text {DS}} - {V} _{\text {GS}}$ loops due to trapping/detrapping, opposite hysteresis to the NC switching are also observed. The NC transistor has much steeper SS compared to the device dominated by the trapping/detrapping process. Statistical results show that only 10% of devices are dominated by the NC effect, and the density of defects in ferroelectric needs to be reduced to improve the yield of NC transistors.

We report a comparative investigation of the negative capacitance (NC) Ge pFETs with different thicknesses of HfZrO x (HZO). Although the NC transistors with 6.6 nm HZO exhibit the sub-60 mV/decade subthreshold swing, the hysteresis inevitably occurs. The hysteresis-free characteristics are demonstrated in the NC Ge pFETs with 4.5 and 3.7 nm HZO. The influence of postannealing temperature on device performance is dependent on the thickness of HZO. With the postannealing at 450 °C, NC transistors with 4.5 and 3.7 nm HZO achieve 23% and 11% ${I}_{\textsf {DS}}$ improvement, respectively, over the control devices, at a ${V}_{\textsf {GS}}$ – ${V}_{\textsf {TH}}$ of −1.0 V and a ${V}_{\textsf {DS}}$ of –0.05 V. However, a higher postannealing temperature of 550 °C leads to the significant degradation in NC device with 4.5 nm HZO compared with the control device. It is further observed that, with the fixed HZO thickness and postannealing temperature, ${I}_{\textsf {DS}}$ of the NC Ge pFETs is improved as the ${C}_{G}$ peak gets increased.

We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrOx (HZO) by changing the post annealing temperature. As annealing temperature varies from 350 °C to 450 °C, HZO exhibits a significant increasing in the ratio of remnant polarization Pr to coercive field Ec, which results in the improvement of the magnitude of ferroelectric NC CFE, therefore contributing to the reduction of hysteresis of the ferroelectric NC Ge transistors. It is also reported that the NC Ge transistor annealed at 450 °C has a small hysteresis of 0.10 V, and achieves the improved SS and IDS compared to control device without HZO.

We report a comparative study of the negative capacitance (NC) Ge pFETs with HfZrO x (HZO) partially and fully covering gate region. Utilizing the layout with HZO partially covering the gate, the internal voltage gain dV $_{{\textsf {int}}}$ / dV $_{{\textsf {GS}}} > \textsf {10}$ is demonstrated in NC Ge pFETs, which is attributed to the NC effect induced by HZO film. NC transistor demonstrates the hysteresis above 2 V, the sub-60 mV/decade subthreshold swing, and the improved drive current over internal-gated MOSFET. As the area of HZO is increased to fully cover the gate, the increased ferroelectric capacitance ${C} _{{\textsf {FE}}}$ produces the much better capacitance matching between ${C} _{\textsf {FE}}$ and the MOS capacitance of TaN/HfO2/Ge channel, contributing to the elimination of hysteresis of the NC Ge pFET. NC Ge pFETs with the gate fully covered by HZO achieve a much higher gate capacitance peak and a 36% enhancement in drive current compared to the devices with HZO partially covering gate.

Negative capacitance (NC) GeSn pFETs integrated with HfZrO x (HZO) ferroelectric film is demonstrated with sub-20 mV/decade subthreshold swing (SS) over two orders of magnitude of ${I}_{\text {DS}}$ . The ratio of remnant polarization to coercivity in HZO is significantly improved with the increasing of the annealing temperature from 400 °C to 500 °C, which contributes to the effective reduction of hysteresis in ferroelectric NC GeSn transistors. Ferroelectric NC GeSn pFET annealed at 500 °C achieves a hysteresis of 70 mV while maintaining a steep SS dramatically lower than 60 mV/decade, and an improved ${I}_{\text {DS}}$ over control device without HZO.

The negative capacitance (NC) Ge pFETs with different thicknesses of HfZrOx (HZO) are investigated. Although NC transistors with 6.6 nm HZO exhibit a 56 mV/decade subthreshold swing, the hysteresis inevitably occurs. The hysteresis-free characteristics are demonstrated in NC Ge pFETs with 4.5 and 3.7 nm HZO. We also study the impact of annealing temperature on the electrical performance of devices, which shows that the hysteresis reduces with the increasing of annealing temperature. By tuning the parameters of HZO, the NC devices achieve better SS and on-current in comparison with the control transistors.

We demonstrate the negative capacitance (NC) effect of HfZrOx-based field-effect transistors (FETs) in the experiments. Improved I DS, SS, and G m of NCFET have been achieved in comparison with control metal oxide semiconductor (MOS) FET. In this experiment, the bottom MIS transistors with different passivation time are equivalent to the NC devices with different MOS capacitances. Meanwhile, the electrical properties of NCFET with 40 min passivation are superior to that of NCFET with 60 min passivation owing to the good matching between C FE and C MOS. Although SS of sub-60 mV/decade is not achieved, the non-hysteretic transfer characteristics beneficial to the logic applications are obtained.