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In cavity quantum electrodynamics, optical emitters that are strongly coupled to cavities give rise to polaritons with characteristics of both the emitters and the cavity excitations. We show that carbon nanotubes can be crystallized into chip-scale, two-dimensionally ordered films and that this new material enables intrinsically ultrastrong emitter-cavity interactions: rather than interacting with external cavities, nanotube excitons couple to the near-infrared plasmon resonances of the nanotubes themselves. Our polycrystalline nanotube films have a hexagonal crystal structure, ~25 nm domains, and a 1.74 nm lattice constant. With this extremely high nanotube density and nearly ideal plasmon-exciton spatial overlap, plasmon-exciton coupling strengths reach 0.5 eV, which is 75% of the bare exciton energy and a near record for room-temperature ultrastrong coupling. Crystallized nanotube films represent a milestone in nanomaterials assembly and provide a compelling foundation for high-ampacity conductors, low-power optical switches, and tunable optical antennas., Comment: 35 pages, including supplementary information

Moore's law continues to prescribe ever smaller device dimensions with each new device node. While the new device nodes are scheduled at even pace, the innovation required to obtain commensurate device performance is greater with every device node. This increased complexity in the process, while maintaining the momentum of Moore's law, is increasing the pressure on the development teams to increase the learning rate on new processes and their interactions. There have been many publications on mix-and-match lithography to enable early learning. In this technique, one whole device level (often the gate definition) is replaced by a different technology (often e-beam), while all the other levels continue to be patterned using traditional optical lithography. Hybrid lithography, by contrast, is the use of different lithography technologies on a single resist level which enables the marriage of both technology's best properties. In this work, we present hybrid e-beam direct write and optical lithography, enabling high throughput (optical), high-resolution (EBDW), excellent overlay (EBDW) and fast prototyping (EBDW). We will show how IBM has used hybrid lithography to enable early learning on back end of the line (BEOL) processes and on extremely scaled SRAM cells ([email protected]^2) [D.M. Fried, et al., IEDM Proceedings (2004) 261-264].

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged by fluorescence microscopy. Our method offers a manufacturable wafer-scale approach for CMOS-compatible bio-chip platform.

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant pat- terning in the sub-30-nm pitch regime using directed self-assembly (DSA) line-space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck tem- perature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal-oxide-semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node. © 2013 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.12.4 .041305)

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.

Critical lithographic dimensions will soon place particularly severe demands on the performance of chemically amplified (CA) resists. Although Extreme Ultraviolet (EUV) and 193 nm (immersion interferometric) lithographic results have demonstrated half pitch imaging down to 35 nm there is nonetheless a concern that image blur due to acid diffusion will begin to seriously impact the utility of CA photoresists. Previously we demonstrated that low activation energy resists and E-Beam lithography can be used to print line/space arrays with resolution approaching 20 nm. We described the factors impacting the reactivity of ketal/pHOST based resists and compared the attainable resolution under different processing conditions. In this report we describe studies on acid diffusion emphasizing the role of water in low Ea systems. We also discuss methods for the control of water absorption in low Ea resists.

A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V/sub T/) and cell beta ratio (/spl beta/) are optimized for cell stability at these aggressive ground rules. The 0.143 /spl mu/m/sup 2/ 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V/sup DD/=1.0 V.

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET. >

KRS-XE, a high performance chemically amplified photoresist designed specifically for e-beam mask making applications, has been enhanced to achieve reduced “footing” on chrome oxide surfaces while still maintaining the original lithographic characteristics that make KRS-XE a promising mask making candidate. These attributes include high resolution, superior bake latitudes, high vacuum stability, coated shelf life of greater than 2 months, and, most notably, the absence of a post exposure bake. In conjunction with the footing reduction the requisite sensitivity requirement of

We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.

Graphene is a very promising candidate for applications in flexible electronics due to its high carrier mobility and mechanical flexibility. In this paper, we present results on graphene RF devices fabricated on polyimide substrates with cutoff frequencies as high as 10 GHz. Excellent channel mobility and current saturation are observed in graphene long channel devices on polyimide. Graphene devices on polyimide also show very good temperature stability from 4.4 K to 400 K and excellent mechanical flexibility up to a bending radius of 1 mm. These demonstrated properties make graphene an excellent candidate for flexible wireless applications.

The authors report on a hybrid lithography process that integrates electron beam lithography (EBL) and optical photolithography. To maximize resolution and density, the EBL exposure is performed using a hydrogen silsesquioxane-based resist, while the photolithographic exposure is performed using standard positive or negative tone 248nm photoresists. Both exposures take place on a common underlayer consisting of an antireflective coating (ARC). During pattern transfer into the ARC layer, a composite image of the two lithographic exposures is formed creating a robust and versatile etch mask for further pattern transfer into the substrate. They demonstrate the utility of this technique by using it to pattern the active, gate, and wiring levels of complementary metal oxide semiconductor devices and circuits consisting of trigated Fin-based field effect transistors. These devices have a minimum active area pitch of 50nm, minimum gate pitch of 90nm, and achieve densities suitable for 15nm node static random acc...

We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon‐on‐insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal‐over‐gate structure. Mix‐and‐match lithography, including the use of electron‐beam lithography for all critical levels, x‐ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to fa...

Preparation of cross-sectional TEM samples has been completed without use of the normal means of mechanical polishing and ion-milling. Instead, lithographic processing and reactive ion-etching (RIE) were used to define thin walls ranging from 100 to 1000 nm in width which protruded 1 μm from the substrate surface. The substrate was cut into pieces suitable for securing them into a standard double-tilt holder so that the etched walls were exposed to the electron beam and images could be formed. Samples have been made using both electron beam and optical lithography with different dry etching processes to define thin walls of composite layers of Si, Si 3 N 4 and SiO 2 and also a thin film of Al-Cu(2 wt%). The results present a promising new method for preparation of cross-sectional TEM samples that is less labor-intensive and more productive than mechanical polishing and ion-milling.