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For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high thermal conductivity, hence SHEs are improved. In order to validate the HGD, technology computer-aided design (TCAD) simulation is performed through Synopsys Sentaurus three-dimensional (3D) tool. As a result, when the HGD is adopted in GAA MOSFETs, SHEs can be significantly improved from 498 K to 415 K. In addition, suppression of gate current, more than 2 orders, is also achieved because of bigger bandgap of SiO2 in HGD. Consequently, this structure takes advantage of higher thermal conductivity and bigger bandgap of SiO2, and higher permittivity of HfO2 for improving SHEs and gate leakage current.

In this article, an investigation has been performed to statistically analyze the entire subthreshold characteristics of tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV). Firstly, the current variations are evaluated through turn-on voltage ( ${V} _{\mathrm{ ON}}$ ) and threshold voltage ( $V_{T}$ ) with help of technology computer-aided design (TCAD) simulation. Secondly, the variation of $V_{T}$ and ${V} _{\mathrm{ ON}}$ are quantitatively analyzed by coefficient of determination ( ${R} ^{2}$ ) in the regression analysis. The ${R} ^{2}$ values are extracted according to the divided the gate prats. Finally, it is confirmed that the WFV of the gate parts causes the current variation in areas where tunneling is varied mainly according to the gate bias.

Composite honeycomb sandwich structure is widely used for aircraft structures such as control surfaces, radomes, engine cowls, and aircraft interior structure because of its lightweight and high strength characteristics. One of the disadvantages of honeycomb sandwich structure is that they are prone to fluid intrusion. The purpose of this study is to determine if the structural properties of honeycomb core are affected by contact with a fluid. The test specimens were manufactured of fiberglass prepreg for the facesheets and Nomex® honeycomb core for the core material in accordance with ASTM C-365/365M. Test specimens were soaked in several different kinds of fluids, such as aircraft fuel, turbine engine oil, hydraulic fluid, and water for a period of 60 days. Some of specimens were tested right after soaking period ended, and some of them were dried before they were tested. A flatwise compressive test was performed, and the test results were analyzed to determine how the contact with aircraft fluids affected the compressive strength of the Nomex® honeycomb core and how the strength was recovered when the specimens were dry. In addition, the investigation of de-bonding between facesheet and core material after soaking was performed to support the study.

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (&sigma, Vturn-on) of 20.1 mV, and it was reduced by &minus, 26.4% for the DG TFET and &minus, 80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending on the gate voltage, the three variations occur in transfer curves. The first one is the on-state current (ION) variation, the second one is the hump current (IHUMP) variation, and the last one is ambipolar current (IAMB) variation. According to the simulation results, the ION variation is sensitive depending on the size of the tunneling region and could be reduced by increasing the tunneling region. However, the IHUMP and IAMB variations are relatively irrelevant to the size of the tunneling region. In order to analyze the cause of this difference, we investigated the band-to-band tunneling (BTBT) rate according to WFV cases. The results show that when ION is formed in L-shaped TFET, the BTBT rate relies on the WFV in the whole region of the gate because the tunnel barrier is formed in the entire area where the source and the gate meet. On the other hand, when the IHUMP and IAMB are formed in L-shaped TFET, the BTBT rate relies on the WFV in the edge of the gate.

In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.

This paper proposes a one transistor dynamic random access memory (1T DRAM) with local partial insulator (LPI) to increase data retention time. Proposed 1T DRAM cell has improved retention characteristics because LPIs inhibit stored carrier movement with high energy barrier. Definition of retention time in the proposed 1T DRAM is introduced at hold '0' state. Device optimization with parameter variation is investigated with device simulation. As the barrier length increases, retention characteristics can be improved but also it causes a decrease in the I1/I0 current ratio. Increase of LPI length improve retention characteristics but reduce I1/I0 current ratio. It was confirmed that the retention characteristics were improved as the hold bias was decreased. Finally, the retention characteristics were optimized when the LPI was precisely formed at the junction boundary.

In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage (Von) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first time. These variations occur because oblique etching slope makes various elliptical-shaped channels in MBC-TFET. Since TFET is promising candidates to succeed metal-oxide-semiconductor FETs (MOSFET), these variation effects have been compared to MOSFET. Furthermore, Ge homojunction TFET, one of the solutions to increase on-state current in TFET and improve SS also has been simulated using technology computer-aided design (TCAD) simulation. The results would be worth reference for future study about GAA NW TFETs.

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.

In this report, a novel tunnel field-effect transistor (TFET) named &lsquo, F-shaped TFET&rsquo, has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET.

Piled rafts are increasingly used for various structures due to the enhanced load-carrying capabilities of raft and piles combined as a single structural unit. In this study, an experimenta...

We integrated the high-speed synchrotron X-ray phase-contrast imaging (PCI) with a modified Kolsky compression bar loading platform to visualize the dynamic failure processes of cross-ply glass fiber reinforced composites (GFRCs). Four S-2 glass/SC-15 composite specimens were prepared, having similar thicknesses but different stacking sequences, namely as [012/9012], [9012/012], [08/908/08], and [908/08/908]. Three-dimensional synchrotron X-ray computed tomography and scanning electron microscopy (SEM) were employed to examine the microstructures and quantify the fiber volume fractions. Each specimen was notched and subjected to a dynamic three-point flexural loading. The onset of cracking close to the notch tip, crack propagation in 0° or 90° plies and their interface, crack opening, and ultimately failure of the specimen were captured by high-speed synchrotron X-ray PCI. Additional dynamic experiments were performed to determine the average time when the stress wave propagated through the specimen and correlate the X-ray images with the specimen's force-deflection response. Finally, the surface morphology of each specimen after the dynamic loading was imaged by SEM. Comparison between real-time X-ray images and post-fracture SEM images demonstrated the capability of the X-ray method to record damage evolution inside composites. Furthermore, the high spatial and temporal resolutions of the X-ray setup and edge enhancement by PCI enabled the identification of microscale damage features within 1 μs. Two damaging processes were identified, crack growth was quantified, and fracture toughness of the composites was evaluated. The method is deemed useful to reveal microscale damage mechanisms and track cracking behaviors inside cross-ply GFRCs under dynamic loading in real time.

We report the application of high-speed synchrotron X-ray phase contrast imaging (PCI) in real-time damage characterization for glass fiber reinforced composites (GFRCs) subjected to dynamic loading. Dynamic single-edge notched bending (DSENB) experiments on pre-notched S-2 GFRCs were performed on a modified Kolsky compression bar. During loading, the synchrotron X-ray beam penetrated through the composite specimen from the side to detect damage evolution inside the material. Entire dynamic events were recorded by a high-speed camera as image sequences.0° and 90° unidirectional and cross-ply composites were investigated. An optical imaging technique was also employed to capture similar dynamic events in comparison with the radiographic imaging. It is demonstrated that high-speed X-ray PCI had sufficient phase contrast to characterize a crack initiation at a 20-μm spatial resolution within 920 ns and track the crack geometry during propagation, thereby providing reliable data to quantify the dynamic damage resistance of GFRCs. Furthermore, being capable of recognizing microscopic damage-related features at a sub-10-μm resolution, high-speed X-ray PCI provided fundamental material failure mechanisms to reveal the essential of macroscale structural failure of composites. It can also track the damage evolution inside and between individual plies of laminated composites. However, current high-speed X-ray PCI technique only supports in-situ observation and the high timing and spatial resolutions are limited within a field of view of ~2.5 mm in square, preventing its application in the three-dimensional and larger-area damage detection for GFRC structures.

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF), ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group&rsquo, s results.

The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and its electrical characteristics are compared to other TFET structures. From two-dimensional (2-D) device simulation results, it is confirmed that the Si/Ge heterostructure source junction improves Ion and SS characteristics by using the direct band-to-band tunneling current. Furthermore, the proposed structure shows suppressed ambipolar behavior since the Ge/Si heterostructure is used at the drain junction.

In conventional LEDs, a mesa-structure is usually used and it causes the current to be overcrowded in a specific region. We propose a novel structure of GaN-based LED to overcome this problem. In order to distribute the current in an active region, a spreading pad is inserted at the p-type region in the GaN based LED device. The inserted spreading pad helps the current flow because it is more conductive than the p-type GaN layer. By performing electrical and optical simulations, the effects of the spreading pad insertion are confirmed. The results of electrical simulation show that the current spreads more uniformly and more radiative recombination is produced as well. Moreover, from the optical simulation, it is revealed that the ITO is less absorptive material than p-GaN if the condition of specific wavelength sources is satisfied. Considering all of the results, we can conclude that the luminescent power is enhanced by the spreading pad.

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

Current crowding problem can worsen the internal quantum efficiency and the negative-voltage ESD of InGaN-based LEDs. In this paper, by using photon emission microscope and thermal emission microscope measurement, we confirmed that the electric field and the current of the InGaN-based LED sample are crowded in specific regions where the distance between p-type metal contact and n-type metal contact is shorter than other regions. To improve this crowding problem of electric field and current, modified metal contact geometry having uniform distance between the two contacts is proposed and verified by a numerical simulation. It is confirmed that the proposed structure shows better current spreading, resulting in higher internal quantum efficiency and reduced reverse leakage current.

Control of threshold voltage (V T ) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For V T -modulation larger than 100 mV, heavy ground doping over 1×1020 cm -3 or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common V T -control scheme when these devices are co-integrated.

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased, this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on&ndash, off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

The Bladder Assisted Composite Manufacturing (BACM) technique allows fabrication of complex hollow composite geometries. However, traditional bladder manufacturing methods require multiple steps and a master geometry which increases the cost and the manufacturing time. Hence, additively manufactured bladders are presented as an alternative solution to bladders manufactured through traditional methods. The use of printed bladders is demonstrated by consolidating and curing a composite part made out of an aerospace grade composite prepreg material, IM7/8552. Bladders are additively manufactured using the Fused Deposition Modeling (FDM) technique with Thermoplastic Polyurethane (TPU). Based on the results of a thermomechanical investigation of the TPU, a two-step curing cycle for manufacturing a composite part with IM7/8552 prepreg was designed. The part consolidation achieved with this method was characterized by measuring void content and comparing it to the void content in a sample cured in a standard autoclave process. The low void content achieved with the BACM method demonstrated the potential of this technology for providing bladders for short production runs or prototyping.

The light-emitting diode (LED) with an improved hole injection and straightforward process integration is proposed. p-type GaN direct hole injection plugs (DHIPs) are formed on locally etched multiple-quantum wells (MQWs) by epitaxial lateral overgrowth (ELO) method. We confirm that the optical output power is increased up to 23.2% at an operating current density of 100 A/cmsup2/sup. Furthermore, in order to identify the origin of improvement in optical performance, the transient light decay time and light intensity distribution characteristics were analyzed on the DHIP LED devices. Through the calculation of the electroluminescence (EL) decay time, internal quantum efficiency (IQE) is extracted along with the recombination parameters, which reveals that the DHIPs have a significant effect on enhancement of radiative recombination and reduction of efficiency droop. Furthermore, the mapping PL reveals that the DHIP LED also has a potential to improve the light extraction efficiency by hexagonal pyramid shaped DHIPs.

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field- effect transistor (I-HTFET) adopting Ge-AlxGa1-xAs- Ge system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2). Index Terms—Tunneling field-effect transistor (TFET), Type-I heterojunction, narrow bandgap material, high mobility, simulation, nanowire, high performance (HP) logic technology

A simple method of measurement which can estimate the recombination coefficients and the internal quantum efficiency (IQE) in GaN-based light-emitting diodes (LEDs) has been developed. The proposed method uses optical power decay, which can reflect real operational circumstances. The method, which is based on the electro-luminescence, is expected to extract values of the IQE in GaN-based LEDs effectively.

An improved rate equation model for GaN-based LEDs considering the effective volume of the active region is proposed. Through numerical simulations, it is confirmed that the IQE, especially efficiency droop is related with small effective volume. Also, we confirmed that the effective volume is controlled by polarization charge, the barriers between the quantum wells, and current density. We also developed a fast and reliable method for extracting the recombination coefficients and the IQE of the GaN-based LEDs by measuring transient characteristics and considering the effective volume. (C) 2014 Optical Society of America

In order to improve the internal quantum efficiency of GaN-based LEDs, a LED structure featuring a p-type trench in the multi-quantum well (MQW) is proposed. This structure has effects on spreading holes into the MQW and reducing the quantum-confined stark effect (QCSE). In addition, two simple fabrication methods using electron-beam (e-beam) lithography or selective wet etching for manufacturing the p-type structure are also proposed. From the measurement results of the manufactured GaN-based LEDs, it is confirmed that the proposed structure using e-beam lithography or selective wet etching shows improved light output power compared to the conventional structure because of more uniform hole distribution. It is also confirmed that the proposed structure formed by e-beam lithography has a significant effect on strain relaxation and reduction in the QCSE from the electro-luminescence measurement.

We have investigated the non-radiative recombination of GaN-based light-emitting diodes (LEDs) using electroluminescence (EL) and cathdoluminescence (CL) techniques. Comparing between EL and CL measurements, we can map the defects causing non-radiative recombination centers. At first, same size mapping techniques of these two measurements show defect-assisted non-radiative recombination. And enlarged CL images give more detail contents about this mechanism. It is concluded that the image mapping of EL and CL in GaN have a strong correlation between the two techniques, and this result shows that non-radiative recombinations are mainly affected by defects of GaN LEDs.

We have investigated the non-radiative recombination of GaN-based light-emitting diodes (LEDs) using electroluminescence (EL) and cathdoluminescence (CL) techniques. Comparing EL and CL measurements, we can map the defects causing non-radiative recombination centers. Also we have researched wet etch effect of Indium-Tin-Oxide (ITO) layer measuring CL technique. The more emissive region of EL measurement has the higher CL intensity in main band-edge (BE) peak in CL measurement, but the less emissive region also has lower CL intensity in BE peak and also defects-assisted emission peaks in other wavelengths and energy levels like yellow-luminescence (YL). It is concluded that the advantages of EL and CL image mapping of defects in GaN, establishing a strong correlation between the two techniques, should be very beneficial for further validation of the two techniques for GaN LEDs.

While a tunneling field-effect transistor (TFET) is an attractive candidate for sub-20 nm ultra-low-power device, high I ON /I OFF and on-current are rarely reported with the deep-submicron structures. In this study, we propose a practical novel TFET structure with vertical channel and Ge junction, which shows high current ratio, low subthreshold swing and relatively high current even when the minimum device dimension is smaller than 20 nm. To find the optimum design, the off-state injection of a short-channel TFET and optimization of the source-side junction are studied by simulation.

In this study, the influence of sidewall thickness on the threshold voltage and on-current of L-shaped Impact-ionization metal-oxide-semiconductor transistor (I-MOS) is investigated. For the sidewall thickness in the range of 10 nm to 20 nm, the devices of thicker sidewall show lower on-current and higher threshold voltage. This is because the electron concentration between the channel and the most active ionization region rapidly decreases as the sidewall gets thicker. As a result, a precise control of sidewall formation is needed in fabricating L-shaped I-MOS devices. Also, obtaining the required on-current and reliability at the same time, as well as suppressing device variability due to sidewall thickness variation, is expected to be challenging.

In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C

In this work, a novel structure for GaN-based LED featuring p-AlGaN trench in the MQW is proposed. Through a numerical simulation, it is confirmed that the proposed structure shows much uniform hole distribution in the MQW than that of the conventional structure, because holes are injected efficiently into the MQW along the p-AlGaN trench. We also confirmed that efficiency droop is reduced and the IQE is improved about 12% when 1 A current flows because of the improved hole distribution. In order to optimize the physical parameters of the p-AlGaN trench, the IQE and the operating voltage are analyzed when the width of the p-AlGaN trench and the distance between the p-AlGaN trenches are changed. In addition, a simple fabrication process for manufacturing the proposed structure is also suggested.

A reversible increase in the current of InGaN-based blue LEDs is observed when constant forward voltage is applied. This characteristic is assumed to be the result of trapping process, and a trap activation energy of 0.30 eV is extracted. Through a numerical simulation, it is confirmed that the multi-quantum well (MQW) barrier height is reduced by the hole trapping process and that the current is increased by lowering this barrier. We also confirmed the effect of this trap on the optical characteristics of InGaN-based blue LEDs by a numerical simulation and measurement.

In this study, the characteristics of the nitride-based blue light emitting diodes (LEDs) having different indium contents multiple quantum barriers were analyzed numerically. The carrier concentrations in the quantum wells (QWs), energy band diagrams, radiative recombinations were investigated. In x Ga1-x N with different indium-composition multiple quantum barriers (QBs) instead of GaN QBs were designed to improve hole transport and radiative recombination. The simulation results indicate that LEDs have a better hole transport in the active regions and uniformity of hole concentration over the conventional LED with GaN QBs. Consequently, the luminescence power of proposed structure was enhanced about 60 times at 3.0 V.

A structure of a tunneling field-effect transistor (TFET) featuring an extremely thin body, a double-gated vertical channel, and a source design to maximize the drive current is proposed and optimized on the basis of technology computer-aided design (TCAD) simulation. The field-coupling effect at the double-gated thin-body channel and an engineered tunneling barrier are implemented to maximize the operation current of the device. Weak current drivability under a small drain bias and the directionality of current flow are the expected challenges in building logic circuits with TFETs. A co-integration scheme to build vertical-channel TFETs and metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed as the solution. A new low-power design using the co-integration scheme is suggested.

Single-electron transistors (SETs) with an electrically formed Coulomb island are proposed and fabricated on the basis of the sidewall patterning on the recessed channel structure. The fabricated device is based on a silicon-on-insulator (SOI) wafer. The quantum dot (QD) is caused by the electrically induced tunneling barriers with n-doped polycrystalline silicon (poly-Si) sidewall gates on the active surface. These devices with side gates are more advantageous in terms of the room-temperature operation and controllability of oscillation peaks for application circuits. This is because the dimensions of the Coulomb island and oscillation peak are modified by the side gate bias. The side gate dependence of the fabricated SET with a recessed channel structure is characterized through a device simulator.

In this work, we have fabricated and characterized the dual gate single-electron transistors (DG-SETs). This device has recessed channel and underlapped source/drain structure. Fabrication flow and device structure are described as well as operation schemes. Clear Coulomb oscillation peaks and negative differential trans-conductance curve are observed at room temperature (300 K). Measurement results obtained at period of Coulomb oscillation is 0.9 V due to an ultra-small control gate capacitance, and oscillation peaks are shifted through the sidewall gate bias. Also, in order to confirm that single electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the silicon-on-insulator (SOI) active, room temperature measurement results for device with different parameters is compared.

We have fabricated single-electron transistors (SETs) with a recessed channel structure using a thermal oxidation process for decreasing the size of quantum dots (QDs). Moreover, the QDs are defined on a one-dimensional silicon nanowire by two tunneling barriers induced through thermal oxidation. Also, for decreasing the control gate capacitance, the dimension of the control gate depends not on the electron beam or photolithography method. The control gate is formed by the controllability of chemical vapor deposition (CVD). Owing to this small capacitance, we have clear Coulomb oscillation peaks and negative differential trans-conductance curves at room temperature. The oscillation period of the fabricated device is approximately 1.9 V.

In this paper, we propose a novel fin and recess-channel metal oxide semiconductor field effect transistor (MOSFET) for sub-50 nm dynamic random access memory (DRAM) cell application. Also, it is compared with the recess-channel-array transistor (RCAT). In the proposed device, a silicon fin region is added to the recessed channel MOSFET. Thanks to the additional current path through the silicon fin with the wide source/drain width, the FiReFET shows excellent current drivability. To reduce gate-induced drain leakage (GIDL) current, we adopt an underlapped device structure. As a result, it is found that the optimized underlap structure helps to prevent the OFF state leakage current induced by the increase of the gate work function.