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Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10-30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 10(7). The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 microm, and decreased exponentially for gate lengths exceeding 1 microm.

The further scaling of silicon devices will hit some roadblocks in the future that may not be overcome by standard technology. The introduction of new materials into silicon technology may help for a while, but integration issues have to be solved in advance. Improvements can, however, also be achieved by new material configurations like nanocrystals that are not formed by subtractive patterning techniques but by self-organized bottom-up approaches. In this paper, we address the prospects for nanoelectronics to exploit the tremendous possibilities of carbon nanotubes (CNTs). A brief introduction of the CNT basics and growth methods will be given. A comparison of state-of-the-art silicon MOSFETs with CNT-FETs highlights the significantly better performance of CNT devices. However, the patterning of CNT devices is still an unsolved problem. Some of the most promising fabrication techniques are assessed with respect to integration into a silicon-like technology. Finally, a new device is presented that circumvents the selection and placement problems of CNTs for stand alone transistors.

The semiconductor industry is expecting extraordinary technological challenges, so the readiness to integrate exotic materials with superior properties into microelectronic chips is increasing and new concepts are attracting more interest. This paper reviews recent research developments aimed at the design of carbon nanotube (CNT)‐based vertical interconnects. We introduce our concept for the integration of CNTs into microelectronic chips that is based on a combination of conventional technology, advanced processing methods (lithography and deposition), and self‐aligned processes.

This paper presents an overview of the issues related to the integration of carbon nanotubes into microelectronics systems. Particular emphasis is placed on the use of carbon nanotubes as on-chip wiring (interconnects) and active devices (transistors), the two main building blocks of current semiconductor circuits. The properties of state-of-the art devices are compared in order to test the viability of replacing silicon-based components with carbon nanotubes. Further, the problems associated with the construction of nanotube-based devices are discussed.

The reaction of multi-walled carbon nanotubes (MWCNT) with xenon difluoride has been studied and compared with the results from experiments with elemental fluorine. A low level fluorination of MWCNTs was achieved at ambient temperature under the influence of light. The outer shells of the nanotubes were converted into a fluorine containing coating that did not significantly affect the electrical conductivity. Fluorination with xenon difluoride was found to be partly irreversible, contrary to previous findings.

Planar field effect transistors (FET) consisting of a large number of parallel single-walled carbon nanotubes (SWCNT) have been fabricated that allow very high on-currents of the order of several milliamperes and on/off ratios exceeding 500. With these devices it is demonstrated, for the first time, that SWCNTs can be used as transistors to control macroscopic devices, e.g., light emitting diodes and electromotors. Those transistors were fabricated by a very simple process that is based on the catalytic chemical vapor deposition (CCVD) growth of SWCNTs at low temperatures, a single lithographic step to define the source and drain contacts, and a bias pulse to eliminate the metallic SWCNTs.

The outstanding performance of carbon nanotubes (CNTs) as interconnects and microelectronic devices has been shown in a number of experiments on hand-picked demonstrators. However, for implementation parallel manufacture, which involves the precise placement and the simultaneous control over the properties of millions of CNTs with microelectronic compatible processes is required. Various concepts for the large-scale integration of CNT-based electronics are compared in this presentation. One of them, catalyst mediated CVD growth, allows the direct growth of CNTs on silicon substrates. Methods for structuring the substrates and the catalyst materials on wafer scale as well as the influence of the process parameters are discussed in terms of reproducibility and uniformity. Furthermore, the synthesis of single, isolated multiwalled CNTs with lithographically defined diameters and locations has been established. This resembles the creation of vertical interconnects consisting of individual and multiple multiwalled CNTs. From this base, a concept for the assembly of CNT based, vertical, surrounding-gate transistors is presented.

A comparison of different catalysts (Ni, Co, Fe/Mo) has been performed in order to minimize the growth temperature for single-walled carbon nanotubes (SWCNTs). Dense SWCNT networks have been synthesized by thermal chemical vapor deposition (CVD) at temperatures as low as 600 °C using Ni catalyst layers of approximately 0.2 nm thickness. The dependence of the SWCNT growth on the most important parameters will be discussed exemplarily on the Ni catalyst system. On the basis of experimental observations, a phenomenological growth model for CVD synthesis of SWCNTs is proposed which is based on the interactions between the catalyst and its support. Further, it is suggested that only surface diffusion of hydrocarbons on the catalyst support or along the CNTs can explain the fast growth rates of SWCNTs during CVD synthesis.

As the semiconductor industry faces increasing technological and financial challenges, new concepts have to be assessed. The extraordinary characteristics of carbon nanotubes make them a promising candidate for applications in micro- and nanoelectronics. Catalyst mediated CVD growth is very well suited for selective, in-situ growth of nanotubes compatible with the requirements of microelectronics technology. This deposition method can be exploited for carbon nanotube vias. Semiconducting single-walled tubes can be successfully operated as carbon nanotube field-effect transistors (CNTFETs). A simulation of an ideal vertical CNTFET is presented and compared with the requirements of the ITRS roadmap. Finally, we compare an upgraded CNTFET with the most advanced silicon MOSFETs.

Individual multi-walled carbon nanotubes (CNTs) were deposited onto microelectrodes and embedded in nickel to achieve low-ohmic contact resistances. Electroless deposition of nickel onto gold/iron, palladium, and cobalt microelectrodes was used to form electrically stable bonds at the interfaces between the electrodes and CNTs. Resistance measurements showed that the contact resistances of the CNTs on gold/iron and palladium were significantly improved by nickel embedding, whereas no further improvement was found for the CNTs on cobalt. Electroless metal deposition is a parallel process providing stable electrical and mechanical contacts between CNTs and metallic microelectrodes.

Carbon nanotubes are of great interest because of their outstanding mechanical, chemical and electric properties. The decoration of multi-walled carbon nanotubes with metal clusters of gold, palladium, iron, cobalt and nickel opens even more applications, especially the growth of complex conductor networks in microelectronic devices.

This work presents a simple and versatile approach for the growth of in-situ contacted single-walled carbon nanotubes (SWCNTs) and subsequent improvement of the contacts using a self-aligned process. We investigated the conditions for the thermal CVD growth of SWCNTs and developed a variety of multilayered metal systems for SWCNT growth at temperatures between 650 °C and 900 °C. The catalytically active layers were either an Fe/Mo bilayer or a Co layer. Further, we report that some of the multilayer systems presented allow lithography free contact improvement by electroless metal deposition.

Carbon nanotubes with their outstanding electrical and mechanical properties are suggested as an interconnect material of the future. In this paper we will introduce nanotubes, compare their electrical properties with equivalent metal wires made of gold and describe our progress in process integration. Multi-walled carbon nanotubes are grown on 6-inch wafers in a batch process. The resulting nanotubes are evaluated with respect to their conductance as single multiwalled nanotubes and in their implementation as interconnects in vias and contact holes.

The chemical modification of multi-walled carbon nanotubes using electrolysis is described. It is found that the evolution of the halogens chlorine or bromine on an anode made from a foil of carbon nanotubes couples halogen atoms to the nanotube lattice. Furthermore, oxygen bearing functional groups, such as hydroxyl and carboxyl groups, are formed at the same time aiding solvation of the nanotubes in water or alcohol without any surfactant. Impurities and low grade modified nanotubes remain insoluble. The halogenated carbon nanotubes can be converted with sodium amide or triphenylmethyllithium to add the corresponding functional groups.

The synthesis of individual carbon nanotubes (CNTs) with controlled diameters at lithographically predefined locations has been achieved. Employing conventional catalyst-mediated chemical vapor deposition (CVD), isolated CNTs were grown out of nanoholes in silicon dioxide created by optical lithography. This allows the precise placement of individual CNTs on substrates. Furthermore, the diameter of each CNT adjusts to the hole size, which makes it possible to control this important property separately for individual CNTs. This approach is a step toward the parallel manufacture of nanotube-based devices in a scalable batch process. In particular, the integration of CNTs into conventional silicon-technology with potential applications as interconnects, transistors, and memory cells becomes possible.

Despite all prophecies of its end, silicon-based microelectronics still follows Moore's Law and continues to develop rapidly. However, the inherent physical limits will eventually be reached. Carbon nanotubes offer the potential for further miniaturization as long as it is possible to selectively deposit them with defined properties.

Carbon nanotube field-effect transistors with sub 20 nm long channels and on/off current ratios of > 1000000 are demonstrated. Individual single-walled carbon nanotubes with diameters ranging from 0.7 nm to 1.1 nm grown from structured catalytic islands using chemical vapor deposition at 700 degree Celsius form the channels. Electron beam lithography and a combination of HSQ, calix[6]arene and PMMA e-beam resists were used to structure the short channels and source and drain regions. The nanotube transistors display on-currents in excess of 15 microA for drain-source biases of only 0.4 Volt., Nano Letters in press

New results on the planar growth of single‐walled carbon nanotubes (SWCNTs) by catalytic chemical vapor deposition (CVD) at low temperatures will be reported. Optimizing catalyst, catalyst support, and growth parameters yields SWCNTs at temperatures as low as 600 °C. Growth at such low temperatures largely affects the diameter distribution since coalescence of the catalyst is suppressed. A phenomenological growth model will be suggested for CVD growth at low temperatures. The model takes into account surface diffusion and is an alternative to the bulk diffusion based vapor‐liquid‐solid (VLS) model. Furthermore, carbon nanotubes field effect transistors based on substrate grown SWCNTs will be presented. In these devices good contact resistances could be achieved by electroless metal deposition or metal evaporation of the contacts.

The unique properties of carbon nanotubes (CNTs) make them promising candidates for electrical conductors in microelectronic devices. The parallel integration of CNTs into processes that are compatible with the requirements of the microelectronic industry will be important for their future application in chip devices. We present lithography‐based processes to create vertical electrical interconnects made of CNTs. The approach involves catalyst and dielectric (insulator) deposition, lithography, standard etch processes, CVD growth of the CNTs, and the structured deposition of metallic top contacts. This paper will discuss the electrical properties of these CNT vertical interconnects and compare them with the requirements of the ITRS roadmap.

Carbon nanotubes (CNTs) have a large variety of properties that make them attractive for applications in microelectronics. A comparison of carbon nanotube field‐effect transistors with silicon MOSFETs shows that CNT devices outperform state‐of‐the‐art silicon transistors. A silicon technology review gives the benchmark for an assessment of the current CNT technology and identifies the growth and placement procedures that are not yet sufficient for industrial applications. Finally, the vertical CNT transistor concept is introduced which deals with the technological problems and opens a new route for 3D integration.

The electronic breakdown and the bias dependence of the conductance have been investigated for a large number of catalytic chemical vapor deposition (CCVD) grown single-walled carbon nanotubes (SWCNTs) with very small diameters. The convenient fabrication of thousands of properly contacted SWCNTs was possible by growth on electrode structures and subsequent electroless palladium deposition. Almost all of the measured SWCNTs showed at least weak gate dependence at room temperature. Large differences in the conductance and breakdown behavior have been found for "normal" semiconducting SWCNTs and small band-gap semiconducting (SGS) SWCNTs., Comment: submitted to Journal of Applied Physics

The integration of carbon nanotubes (CNTs) into conventional silicon-technology with potential applications as interconnects, transistors, memory-cells, and sensors is an promising goal. Theoretical and experimental results indicate that CNT-based devices can outperform conventional silicon microelectronics. Concepts for the creation of vertical interconnects and transistors made out of CNTs, which allow a large scale integration, are presented. A vital step for their realization is the synthesis of individual CNTs with controlled diameters at lithographically predefined locations. Employing catalyst mediated Chemical Vapor Deposition (CVD) isolated CNTs have been grown out of holes in silicon dioxide which have been created by optical lithography. This allows the precise placement of individual CNTs on silicon substrates. Furthermore, the diameter of each CNT adjusts to the hole size, which makes it possible to control this important property separately for individual CNTs. In combination with the vertical integration concept those findings constitute a milestone in the parallel manufacture of nanotube-based devices with scalable batch processes.

An important prerequisite for the implementation of carbon nanotubes (CNTs) in microelectronic circuits is the evaluation of their electronic properties. For this, the generation of low‐ohmic electrical contacts between CNTs and metallic circuit lines is crucial. We describe a parallel process which does not rely on e‐beam lithography and yields self‐aligned, low‐ohmic contacts on wafer scale. CNTs that are spray deposited on metallic test structures created by optical lithography are subsequently embedded by electroless metallization and annealed. With this method we are able to simultaneously lower the contact resistance of an unlimited number of CNTs. The reduction of the contact resistance depends on the metals involved and the annealing process. This new method enables the statistical evaluation of the CNT quality dependence on synthesis conditions.

We report on the CVD‐growth of single‐walled carbon nanotubes (SWCNTs) and their electrical characterization. Growth between catalyst covered Mo‐pads yields in‐situ contacted SWCNTs. With this approach, only one level of conventional photolithography is required to obtain SWCNTs ready for field‐effect measurements. The SWCNT yield depends strongly on the catalyst composition and growth conditions, which have been investigated over a wide range. The growth of isolated SWCNTs in lithographically defined holes is also demonstrated. This is the first step towards the realization of surrounding gate vertical SWCNT field‐effect transistors (VCNTFET), which are expected to outperform future silicon‐based devices.

The remarkable properties of carbon nanotubes (CNTs) make them especially interesting for microelectronic applications including interconnects and devices. The parallel integration of CNTs into circuits using microelectronics compatible processes is critical for their future application and implies the simultaneous processing of billions of CNTs. We present our concepts for CNT-based interconnects and vertical, surrounding-gate transistors for large-scale integration. In order to realise this, the precise placement of CNTs with lithographic methods and the controlled production of CNTs with defined properties is necessary. We demonstrate vertical interconnects (vias) made from multi-walled nanotubes and their electrical characteristics. Further, we show the CVD growth of single, isolated single-walled and multi-walled CNTs at lithographically defined locations suitable for single CNT devices. Self-aligned, single-walled CNT transistors have also been realised and their electrical performance characterised.

Carbon Nanotubes (CNTs) offer extraordinary properties for applications in microelectronics. We assess the methods used to grow CNTs for integration into microelectronics, in particular, metallic carbon nanotubes for vias and interconnects as well as semiconducting CNTs for fieldeffect devices are discussed. State-of-the-art CNTFETs are compared to Si-MOSFETs. A vertical CNTFET (VCNTFET) device concept is presented which offers better growth control, adding a new quality to microelectronics and making real 3-dimensional electronics possible.