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Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to $2\times $ for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity. [ABSTRACT FROM AUTHOR]

This paper presents a comparative analysis of the single-event effect (SEE) sensitivity of Double Data Rate memories from different manufacturers. Two-photon laser testing is performed to extract technological information such as the memory array organization and an estimation of the cell size. SEE laser energy thresholds are compared as well as the impact of the applied power mode. Bitline upsets are experimentally observed and confirmed by an analysis based on Monte-Carlo simulations. Heavy-ion testing results, including various kinds of SEFIs, are presented and discussed. [ABSTRACT FROM PUBLISHER]

This paper presents a simulation and experimental study of the analog single-event transient sensitivity of wide bandwidth operational amplifiers. Architecture effects are presented that could influence ASIC design and COTS selection. [ABSTRACT FROM AUTHOR]

Device simulations of laser induced SEU in an SRAM cell are performed with pulse durations from 100 fs to 100 μs. SEU threshold energy is notably dependent on the pulse duration. Two regimes are identified and modeled analytically and electrically. [ABSTRACT FROM AUTHOR]

A new category of analog single-event transients (SETs) with millisecond-long durations have been experimentally observed in the LM6144 operational amplifier. It is the first time that events with such extreme widths are under investigation in a linear integrated circuit. Relying on heavy-ion broadbeam tests, picosecond pulsed lasers diagnostics, and computer-assisted circuit modeling, we uncover the mechanisms and causes of these anomalous voltage transients. The identification of the problematic area of the IC reveals that the bias/startup circuitry is sensitive to energetic ionizing particles and can be responsible for corrupted circuit operations when subjected to a heavy-ion strike. A circuit hardening solution with minimal impact on the layout and the electrical performances of the op amp are proposed to mitigate this effect. [ABSTRACT FROM AUTHOR]

This paper describes the use of a pulsed laser for studying radiation-induced single-event transients in integrated circuits. The basic failure mechanisms and the fundamentals of the laser testing method are presented. Sample results are presented to illustrate the benefits of using a pulsed laser for studying single-event transients. [ABSTRACT FROM AUTHOR]

Abstract: Various optical defect localization techniques are applied on the same integrated circuits (IC). These circuits were previously stressed by Electro Static Discharges (ESD) to create defects. The results obtained by each technique were analyzed to determine the nature of the defects. The different data are compared to assess their sensitivity and to evaluate the contribution of each technique in a failure analysis flow. [Copyright &y& Elsevier]

Abstract: This study is driven by the need to improve failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus, it is mandatory to understand the behavior of elementary devices under laser illumination, in order to model and predict the behavior of more complex circuits. This paper characterizes and analyses effects induced by static photoelectric laser stimulation (1064nm) on a 90nm technology metal–oxide–semiconductor (MOS) capacitor. On n-MOS capacitor the laser induces interface traps in the low part of the silicon band-gap, contrary to p-MOS capacitor where it is in the upper half part of the gap. It is also shown that electric stress increases the density of such interface traps. [Copyright &y& Elsevier]

Abstract: This paper describes a new technique that uses a 1064nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains. [Copyright &y& Elsevier]

Abstract: Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented. [Copyright &y& Elsevier]