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Optical encryption technology attracts considerable attention in the field of information encryption, information storage, and anti‐counterfeiting. However, optical encryption based on conventional on/off mode still faces issues such as low scalability, ease of cracking, and poor storage capacity; multi‐dimensional and high storage capacity information encryption systems are thus needed. Herein, a programmable information encryption circuit system is demonstrated by constructing a delay light‐emitting diode (LED) array using multi‐color phosphorescent carbon nanodots (CNDs) with versatile lifetimes. The CNDs show adjustable luminescence wavelength and lifetime from 192 to 1148 ms. The programmable delay luminescent circuit provides an intricate framework for meticulously integrating an LED array, enabling the creation of intricate patterns or alphanumeric codes. These intricate designs are engineered to serve as a component of an encryption system, which can be deciphered and unveiled under a specific delay time range. This study demonstrates the feasibility and superiority of the system as a new type of information anti‐counterfeiting encryption technology, providing a new concept for exploring the field of integrated circuit anti‐counterfeiting and encryption. [ABSTRACT FROM AUTHOR]

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 and 100 GHz, with ± 24% and ± 13% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm2 with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm2 and beyond. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

In this article, a matched branch line‐loaded negative group delay (NGD) circuit without resistor is presented firstly, and then an Wilkinson power divider with NGD characteristic is implemented by integrating the NGD circuit and the power divider by using self‐packaged suspended coplanar waveguide (SCPW) technology. The self‐packaged SCPW power divider with NGD characteristic has been fabricated, and the design has been demonstrated by measurement, which indicates that the proposed power divider with NGD characteristic has a measured signal attenuation (S21) of 10.92 dB, a S11 attenuation of 32.1 dB, an NGD time of −2.42 ns, and an isolation of no less than 39 dB at the center frequency, while simple circuit topology, self‐packaging and compact circuit size have also been achieved. [ABSTRACT FROM AUTHOR]

A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction. [ABSTRACT FROM AUTHOR]

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits. [ABSTRACT FROM AUTHOR]

With the increasing adoption of millimeter-waves (mmWave) over cellular networks, outdoor-to-indoor (O2I) communication has been one of the challenging research problems due to high penetration loss of buildings. To address this, we investigate the practicability of utilizing reconfigurable intelligent surfaces (RISs) for assisting such O2I communication. We propose a new notion of prefabricated RIS-empowered wall consisting of a large number of chipless radio frequency identification (RFID) sensors. Each sensor maintains its own bank of delay lines. These sensors which are built within the building walls can potentially be controlled by a main integrated circuit (IC) to regulate the phase of impinging signals. To evaluate our idea, we develop a thorough performance analysis of the RIS-based O2I communication in the mmWave network using stochastic-geometry tools for blockage models. Our analysis facilitates two closed-form approximations of the downlink signal-to-noise ratio (SNR) coverage probability for RIS-based O2I communication. We perform extensive simulations to evaluate the accuracy of the derived expressions, thus providing new observations and findings. [ABSTRACT FROM AUTHOR]

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180 nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analyzed using the Cadence Spectre. • Designing low-power full adders is of paramount importance in modern digital system design. • The swing restored technique was employed to reduce the signal swing at the internal nodes of the full adder circuit, thereby reducing the power consumption and improving the circuit's speed. • This paper presents a novel design of a full adder circuit using the modified swing restored technique for reducing power consumption and enhancing performance. • The full adder cell introduced in this research was designed with 180 nm CMOS process technology. • A comparative study was performed between the proposed circuit and earlier reported circuits, revealing reduced power dissipation in the proposed design. [ABSTRACT FROM AUTHOR]

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology. We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques. • Minimize Leakage Power in Digital Circuits. • A Combination of Body Bias and Multi-threshold CMOS technique for Leakage Power Minimization. • Achieve Higher efficiency as well as Simultaneously Reduce Leakage Power and Propagation Delay in Digital Circuits. • A New method based on Combination of DTMOS Transistor and Body Biasing Technique for Leakage Power Minimization. • A Proper Performance in Different Corners of the Process. [ABSTRACT FROM AUTHOR]

The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation on resistance and capacitance intermixed with resistance variation on vias between them, a very high dimensional design space exploration is necessary to synthesize a representative critical path circuit which is able to provide an accurate performance prediction. To this end, we propose a BEOL-aware methodology of synthesizing a representative critical path circuit, which is able to incrementally explore , starting from an initial path circuit on the post-Si target circuit, routing patterns (i.e., BEOL reconfiguring) as well as gate resizing on the path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of novel techniques: (1) extracting and classifying BEOL configurations for lightening design space complexity, (2) formulating BEOL random variables for fast and accurate timing analysis, and (3) exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. In summary, our synthesis framework is able to reduce the prediction error by 54% and 19% on average over that using the conventional critical path replica and using the conventional method exploiting gate sizing only, respectively. • We propose a BEOL (back-end-of-line)-aware methodology of synthesizing a representative critical path circuit. Precisely, our synthesis framework of critical path circuit integrates a set of the following novel techniques: • Extracting and classifying BEOL configurations for lightening design space complexity. • Formulating BEOL random variables for fast and accurate timing analysis. • Exploring alternative (ring oscillator) circuit structures for extending the applicability of our work. [ABSTRACT FROM AUTHOR]

Without any dummy element for phase compensation, a clock-deskewing circuit (CDC) using a master–slave delay-locked loop (MSDLL) configuration is presented to synchronize the clocks for cascaded core-to-core links. The dual-locking CDC provides mismatch-insensitive compensation of interconnected wires, input/outputs (IOs), and clock buffers. The MSDLL incorporates the digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) to provide a wide range operations. The proposed FCF-VCDL scheme is constructed from the combination of positive and negative gains of different VCDLs. In addition, a power-controlled regime is employed in the FCF-VCDL to adaptively lower the power dissipation. Implemented with 0.18 μm CMOS, the CDC can provide 20 MHz to 2 GHz with the help of FCF-VCDLs. The 2-GHz clock jitter is 6.78 ps (pk-pk), and the total power dissipation is 20 mW under a 1.8-V supply. [ABSTRACT FROM AUTHOR]

This paper presents a new dual-band diode mixer for the X- and K-bands. The proposed mixer consists of a pair of series-connected diodes and a frequency-dependent delay line that operates at 180° and 360° at the X-band of 10.525 GHz and at the K-band of 24.15 GHz, respectively. Without reconfigurable devices such as switches, the proposed mixer operates as a single-balanced diode mixer at the X-band and a subharmonically pumped antiparallel diode mixer at the K-band simultaneously. The designed circuit was implemented in a hybrid microwave integrated circuit using discretely packaged RF components on a microwave printed circuit board. The measurement results showed conversion losses of 6.5 dB and 16.6 dB at the X- and K-bands, respectively. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10−12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a new current-feedback operational-amplifier (CFOA) based first-order voltage mode all-pass filter (APF). The proposed circuit can be used as a tunable time-delay circuit with relatively large time delays. The circuit enjoys low output impedance and, therefore, can be easily cascaded with similar circuits to obtain larger time delays. The functionality of the circuit was confirmed using PSPICE simulation tool and commercially available integrated circuit (AD844). The simulation results show that delay can be tuned from 10µs to 256µs. [ABSTRACT FROM AUTHOR]

A high-precision delay chain circuit integrated in a 0.18- $\mu \text{m}$ CMOS technology working in the frequency bandwidth of 8–18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay cell has larger delay-bandwidth product and is less prone to parasitic capacitances of inductor elements compared with conventional passive second-order APN delay cells. The fabricated chip utilizing the novel delay cell occupies an area of $0.9\times3.6$ mm2 and consumes 115.5- and 13.5-mW dc power from a 3.3-V voltage supply in its high- and low-power modes, respectively. [ABSTRACT FROM AUTHOR]

This brief presents an on-chip autotuning algorithm to reduce the supply voltage sensitivity of digitally controlled delay lines constructed using identical digital buffers. The proposed algorithm tunes a compensator circuit embedded within each buffer to counterbalance the supply sensitivity of the overall delay line regardless of process or mismatch variations. A 3-D IC mismatch-insensitive skew compensation (MISC) architecture employing this delay line is fabricated in 65-nm CMOS and demonstrates robust performance against the buffer supply noise at operating frequencies of 250 MHz to 1 GHz. The rms jitter of this supply-compensated MISC design measures 3 ps in the presence of a 25-mV 1-MHz supply noise at 1-GHz operation, compared to 112.3 ps for the conventional design, whereas the maximum residual skew between the Die-1 and Die-2 clocks measures under 30 ps across the entire MISC frequency range. [ABSTRACT FROM AUTHOR]

A simple, efficient, and low-cost method is proposed to reduce the timing jitter in passively Q-switched microchip lasers by self-injection seeding. A portion of the output pulse of the microchip laser was incident into the fiber delay line, and then, the backward reflection light induced the formation of the pulse. With different lengths of fiber, it was found that the timing jitter of the microchip laser could be reduced effectively when the repetition rate of the microchip laser was about 0.8 times the reciprocal of the delay time. The standard deviation of the microchip laser was reduced from several hundred nanoseconds to less than 181 ps. [ABSTRACT FROM AUTHOR]

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic. [ABSTRACT FROM PUBLISHER]

A 2.5-Gbps/lane receiver bridge chip, which fully supports the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) camera serial interface (CSI)-2, is proposed for a field-programmable gate array (FPGA)-based frame grabber. The proposed receiver bridge chip converts four-lane high-speed data of scalable low-voltage signaling (SLVS) of the MIPI CSI-2 into 32 low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip. In order to achieve this, each data lane of the proposed receiver bridge chip has a 1-to-8 deserializer including a byte synchronizer. Furthermore, an asynchronous delay line per lane compensates the time skew among the five lanes, including a clock lane. A common-gate level shifter (CGLS) with a continuous-time linear equalizer (CTLE) is proposed to improve the voltage fain and bandwidth of the high-speed receiver. The proposed receiver bridge chip is implemented using a 0.11 μm CMOS process with a 1.2 V supply. The area and power consumption of the proposed receiver bridge chip are 5.29 mm2 and 7.2 me/Gbps/lane, respectively. The proposed CTLE of the high-speed receiver achieves the improved peak-to-peak time jitter of 0.3UI at a data rate of 3.0 Gbps/lane. The FPGA-based frame grabber processes the image or video data supplied by a camera sensor with the MIPI CSI-2 by using the proposed receiver bridge chip. [ABSTRACT FROM AUTHOR]

We present the design, operation, and test results of a new integrated time interval (TI) counter that provides high resolution (1.9 ps), low measurement uncertainty (below 4.5-ps rms in advanced measurement modes), and wide measurement range (above 1 h, easily extendable). Fundamental for the counter, TI measurements are simultaneously performed in eight independent channels, while the advanced configuration of input channels improves either the precision (up to 3 ps) or the measurement speed (up to 91.2 \times 10^6 registered events/s). The functional flexibility and high speed are achieved based on the timestamp (TS) principle that makes possible registering on the common time scale events appearing at counter inputs and then measuring the time intervals between any registered events. The high precision is obtained by employing two-stage inner interpolation with an eight-phase clock in the first stage of interpolation and an equivalent time coding delay line in the second one. The time counter is integrated in a single, cost-effective field programmable gate array chip manufactured in a 28-nm CMOS process. [ABSTRACT FROM AUTHOR]

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC’99 and International Work on Logic and Synthesis’05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits. [ABSTRACT FROM AUTHOR]

Cables, printed circuit boards, and VLSI interconnects are commonly modeled as multiconductor transmission lines. Models of electrically long transmission lines are memory and time consuming. In this paper, a robust and efficient algorithm for the generation of a delay-based model is presented. The impedance representation via the open-end matrix Z is analyzed. In particular, the rational formulation of Z in terms of poles and residues is exploited for both lossless and lossy cases. The delays of the lines are identified, and explicitly incorporated into the model. A model order reduction of the system is automatically performed, since only a limited number of poles and residues are included in the rational part of the model, whereas the high-frequency behavior is captured by means of closed expressions that account for the delays. The proposed method is applied to two relevant examples and validated through the comparison with reference methods. The time-domain solver is found to be more accurate and significantly faster than the one obtained from a pure-rational model. [ABSTRACT FROM AUTHOR]

We propose an all-digital on-chip time-domain temperature sensor for system-on-a-chip (SoC) thermal management. For on-chip purposes, the proposed temperature sensor achieves energy- and area-efficient and fast thermal monitoring by adopting a digitally controlled oscillator (DCO) with the frequency divider and XNOR gate to generate temperature-dependent pulse. The frequency divider with the fine delay unit allows DCO of the proposed structure to have a smaller number of delay cells than a conventional open-loop delay line while maintaining resolution. The use of DCO with frequency divider, which consists of three flip-flops, reduced the required delay line length by 16 times. XNOR gate facilitates the fast thermal monitoring by simply providing the temperature-proportional pulse without additional processing. Temperature measurement results are provided with a digital code generated by a simple counter-based time-to-digital conversion. The proposed temperature sensor is fabricated using 0.13- $\mu $ m CMOS technology and achieves a low-energy consumption of 2.3 nJ at a conversion rate of 293 kHz with a resolution of 0.72 °C and an area of 0.036 mm ^{2} . The proposed sensor also obtains a measurement error of −2.4 °C to 2.16 °C from nine test chips over a temperature range of 20 °C–120 °C, which is suitable for SoC thermal management. [ABSTRACT FROM AUTHOR]

To increase contrast in positron emission tomography (PET) images, researchers are investigating detectors that reach below the nanosecond timing resolution. This allows a tight coincidence window which reduces random coincidence counts in the acquired data, as well as to include time-of-flight information into the reconstruction algorithms. With this goal in mind, single photon avalanche diode (SPAD) arrays have been under study for their excellent timing performances. However, their spurious dark counts can blur the start of PET signals where timing information is the most precise and create false starts in the acquisition system, introducing dead time. To minimize these problems in digital SPAD systems using a single time to digital converter (TDC) per PET channel, dark count discriminator circuits are required to reduce timing errors and increase the triggering efficiency in presence of dark counts. This paper compares the performance of a probabilistic and a novel delay line based dark count discriminator. Simulations of a SPAD array investigate the impact of dark counts on triggering efficiency and coincidence timing. Results show that the probabilistic discriminator provides excellent event recovery with regard to dark counts at the cost of some coincidence timing resolution. On the other hand, the delay line discriminator maintains the peak coincidence timing resolution but does not provide as much efficiency at high dark count rate levels. [ABSTRACT FROM PUBLISHER]

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero- \(\textit {V}_\mathbf {GS}\) -load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero- \(\textit {V}_\mathbf {GS}\) -load logic circuits. [ABSTRACT FROM AUTHOR]

The statistical nature of gate delays in current day technologies necessitates the use of measures, such as path criticality and node/edge criticality for timing optimization. Node criticalities are typically computed using the complementary path delay. An alternative approach to compute the criticality using the circuit delay has been recently proposed. In this paper, we discuss in detail, the use of circuit delay to compute node criticalities and show that the criticality thus found is not equal to the conventional measure found using complementary path delay. However, there is a monotonic relationship between them and the two measures can be used interchangeably. We derive new bounds for the global criticality and propose a pruning algorithm based on these bounds to improve the accuracy and speed of computation. The use of this pruning technique results in a significant speedup in criticality computations. We obtain an order of magnitude average speedup for ISCAS benchmarks. [ABSTRACT FROM PUBLISHER]

In this paper, novel photonic delay lines (DLs) using Vernier/non-identical ring resonators (VRRs) are proposed and demonstrated, which are capable of simultaneous generation of multiple different delays at different wavelengths (frequencies). The simple device architectures and full reconfigurability allow the DLs to be integrated with other functional building blocks in photonic integrated circuits to realize on-chip, complex multi-λ microwave photonic signal processors with reduced system complexity. To prove the concept, DLs using VRRs in cascaded and coupled configurations have been fabricated in TriPleXTM waveguide technology, which enables a very low delay-induced loss of approximately 0.18 dB/100 ps. The fabricated DLs demonstrated simultaneous generation of four incremental delays, where a maximum incremental step of 550 ps and a corresponding top delay of 1650 ps were measured for a bandwidth up to 1 GHz. To our knowledge, this is the first report on VRRs for delay generation functionalities. [ABSTRACT FROM AUTHOR]

This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm². With a sampling rate of 4 MHz, the ADC consumes 14/LtW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V. [ABSTRACT FROM AUTHOR]

This work presents a multi-channel, time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10 ps LSB duration, an integral non-linearity range of 3.86 LSB, and an input range longer than 100 \mus. Total time uncertainty (single-shot jitter) is measured to be 19.6 ps at a time difference of 40 ns, and less than 400 ps at a time difference larger than 100 \mus. [ABSTRACT FROM PUBLISHER]

In this paper, we present a new readout circuit with an integrated built-in self-test (BIST) structure for capacitive microelectromechanical system (MEMS). In the proposed solution, instead of commonly used voltage control signals to test the device, charge-controlled stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of structural collapse in the test phase for gap-varying parallel-plate MEMS devices. Measurement results using a prototype fabricated in TSMC 65-nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance. [ABSTRACT FROM AUTHOR]

Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability. [ABSTRACT FROM PUBLISHER]

In this paper, a fast-locking all-digital deskew buffer with duty cycle correction is proposed and implemented. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop to only two input clock cycles in coarse tuning. With the aid of the three half delay lines technique, the mismatch between half delay lines causing the duty cycle distortion can be alleviated by interpolation. A balanced edge combiner to achieve a precise 50% output clock is also presented. A test chip is fabricated in 0.18-\mum technology to demonstrate the feasibility of the proposed architecture. The circuit can accept the input clock rates from 250 to 625 MHz with the duty cycle variation within 30% and 70% to generate 50% output clocks. It preserves the capability of closed-loop control with a small area and power consumption. [ABSTRACT FROM PUBLISHER]

In this paper, we perform the theoretical analysis and experimental demonstration of an on-chip implementation of a Ku-band nanosecond scale time-stretching (TS) system in a 130-nm IBM 8RF CMOS process. The theory of the TS system is applicable to general TS systems. In this study, we explain the impact of the time-bandwidth product (TBP) on practical design considerations and derive the error and distortion of a general TS system based on a dispersive delay line with perfect linear group delay and all pass amplitude characteristic. We also derive the time resolution of a general TS system using both the principle of uncertainty as well as the short time Fourier transform method. This fundamental result enables a designer to understand the qualitative relationship between the TBP and the best possible resolution of the TS system. Finally, we experimentally demonstrate the TS system on chip with nanosecond group-delay variance and 12–16-GHz bandwidth. This demonstration indicates the potential for implementation of more complicated time-scaling signal-processing systems on chip, as well as a quantification of the error and distortion for such systems. [ABSTRACT FROM PUBLISHER]

A large spread of leakage power due to process variations impacts the total power consumption of integrated circuits (ICs) substantially. This in turn may reduce frequency and/or yield of power-constrained designs. Facing such challenges, we propose two methods using power-gating (PG) devices whose effective width can be adjusted during a post-silicon tuning process. In the first method, we consider processors exhibiting substantial core-to-core frequency and leakage power variations while only a global voltage/frequency domain is supported. Since each core in a processor often has its own PG device, the total width each PG device and the global voltage are tuned jointly to maximize the global frequency for a given power constraint. Our experiment demonstrates that the maximum frequency of 2-, 4-, 8-, and 16-core processors is improved by 5%–21%. In the second method, we take rejected dies due to excessive leakage power. We adjust the width of PG devices such that the dies satisfy their given power constraint. Our experiment shows that 88%–98% of discarded dies violating their power constraint are recovered. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed on-chip path delay measurement (OCDM) circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed OCDM circuit can achieve a large delay measurement range with a small quantity of delay stages. A calibration circuit is incorporated into the proposed on-chip path delay measurement technique to calibrate the delay range of the delay stage under process variations. In addition, delay calibration for import lines is conducted to improve the precision of path delay measurement. Experimental results are presented to validate the proposed path delay measurement architecture. [ABSTRACT FROM AUTHOR]

Editors' notes: [ABSTRACT FROM AUTHOR]

The algorithm for synthesis of the multi-tapped meander delay line (MTMDL) topology is proposed in this article. The algorithm is based on search of construction parameters of the MTMDL according to Monte Carlo method. Proposed algorithm was realized as software and tested on 14 nodes computer cluster. Experimental synthesis of lines has shown adequacy of the suggested algorithm. It has been shown that increasing number of nodes in the cluster, synthesis is executing faster and parallel part of the algorithm approaches to 90 percent of total algorithm. It is revealed that the maximal efficiency of the algorithm is achieved when the number of cluster nodes reaches the number of all issued synthesis processes. [ABSTRACT FROM AUTHOR]

This paper presents an improved algorithm for power hardware-in-loop (PHIL) simulation that takes the errors introduced by the interface equipment into account. Through modeling and analysis of a PHIL simulation circuit, which is composed of a voltage-source converter and a simple network, the impact of the bandwidth of the interface amplifier and equipment on the PHIL simulation is examined. Based on the analysis, an improved algorithm is proposed that uses additional interface filters (implemented in hardware and/or software) rather than the use of previously attempted compensation techniques. More stable and accurate results can be obtained by using the new algorithm. The validity of the proposed algorithm is verified through a software case study and hardware case studies. [ABSTRACT FROM AUTHOR]

A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40\times) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 \mu\ m \times \ 800 \mu\ m in 0.13 \mum CMOS. [ABSTRACT FROM AUTHOR]

We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source. [ABSTRACT FROM AUTHOR]

Power switching loss estimation for fast power semiconductor devices requires probe inverse models. Simple corrections of the delay introduced by the probe cables improve the measured waveform, but they are not sufficient. Prior to the construction of the probe inverse models, the authors introduce direct models. Particularly, the classical RLC equivalent circuit reveals a poor model. The “traveling wave,” i.e., Bergeron's approaches, is introduced, which leads to convenient probe inverse models. The validation is obtained between experimental results and simulation. [ABSTRACT FROM AUTHOR]

The increase of operating frequencies requires \bf 3-D electromagnetic (EM) methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by \bf 3-D EM methods and model order reduction (MOR) techniques are used to reduce such a high complexity. When signal waveform rise times decrease and the corresponding frequency content increases, or the geometric dimensions become electrically large, time delays must be included in the modeling. A PEEC formulation, which include delay elements called \tauPEEC method, becomes necessary and leads to systems of neutral delayed differential equations (NDDE). The reduction of large NDDE is still a very challenging research topic, especially for electrically large structures, where delays among coupled elements cannot be neglected or easily approximated by rational basis functions. We propose a novel model order technique for \tauPEEC models that is able to accurately reduce electrically large systems with large delays. It is based on an adaptive multipoint expansion and MOR of equivalent first-order systems. The neutral delayed differential formulation is preserved in the reduced model. Pertinent numerical examples based on \tauPEEC models validate the proposed MOR approach. [ABSTRACT FROM AUTHOR]

A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110\ \mu\m\times\ 105\ \mu\m. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing. [ABSTRACT FROM AUTHOR]