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A novel odd-even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is

A new low-power EEPROM circuit for sensor interface circuit is introduced in this paper. The calibration data and parameter setting data stored in EEPROM can be reloaded automatically by the power-on-reset (POR) technique when the power is on. The module only consumes power during power-on-reset and data changing by status optimization and low-power design. This EEPROM circuit design has been used in a MEMS accelerometer readout circuit verified by 0.35μm CMOS EEPROM process. The results are satisfying in that the module can write and store 25bit data and automatically reloads data within 0.1μs after power-on and then turns to low power mode.

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ?m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5 mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900 e. The power dissipation without the output buffer is about 2.6 mW.

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 mm2. An experimental 130 t 130 RRSCA chip has been fabricated with 1.2-mm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.