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As the complexity of nanocircuits continues to increase, developing tests for them becomes more difficult. Failure analysis and the localization of internal test points within nanocircuits are already more difficult than for conventional integrated circuits. In this paper, a new method of testing for faults in nanocircuits is presented that uses single-photon detection to locate failed components (or failed signal lines) by utilizing the infrared photon emission characteristics of circuits. The emitted photons, which can carry information about circuit structure, can aid the understanding of circuit properties and locating faults. In this paper, in order to enhance the strength of emitted photons from circuit components, test vectors are designed for circuits’ components or signal lines. These test vectors can cause components to produce signal transitions or switching behaviors according to their positions, thereby increasing the strength of the emitted photons. A multiple-valued decision diagram (MDD), in the form of a directed acrylic graph, is used to produce the test vectors. After an MDD corresponding to a circuit is constructed, the test vectors are generated by searching for specific paths in the MDD of that circuit. Experimental results show that many types of faults such as stuck-at faults, bridging faults, crosstalk faults, and others, can be detected with this method.

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram (BDD). First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n+1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m>3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1+[n/(m−1)], for multiplication modulo circuits is n+1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n+1 vectors.

A new approach for detecting multiple faults in digital circuits is presented in this paper, which uses neural network technique to generate the test vectors and to diagnose the multiple faults. First of all, the optimal neural network model corresponding to an arbitrary digital circuit is used. For a logic circuit with m inputs and n outputs, the optimal neural networks having m+n neurons can represent the logic function of the circuit. Secondly, the test vectors of multiple faults in the circuit are obtained by using evolutionary strategies to compute the minimum energy states of the optimal neural network. Thirdly, the multi-layer feed forward network and back propagation algorithm are used to diagnose the multiple faults in the circuit. The design of both network configurations and samples patterns are given in detail. Experimental results show that the approaches proposed in this paper are effective for detecting and diagnosing multiple faults in digital circuits.

A new approach to generate test sets for multiple faults of digital circuits is presented in the paper, which employs neural networks and simulated annealing technique. The neural network models for circuit are built, the test vectors of multiple faults in the circuit can be produced by computing the minimum energy states of the neural networks. An algorithm based on simulated annealing is proposed to compute the minimum states of energy functions, the algorithm has global convergence and has polynomial complexity under a decrement scheme of temperature. Experimental results shows that it is possible to obtain high fault coverage for testable multiple faults with the proposed approach without fault simulation.

A method of devising a universal test set for detecting bridging faults in circuit testable realizations is investigated. The circuit realizations employed use an XOR gate tree construction and generalized Reed-Muller (GRM) expressions of logic functions. It is shown that all AND bridging faults and OR bridging faults in the circuit realization can be detected. The cardinality of the bridging faults test set is (2n+m), where n is the number of variables present in the logic functions, and m is the number of product terms in function expressions. Furthermore, a bridging fault testing method is given for the testable realization of the EXOR-sum-of-products (ESOP) expression of logic functions. The ESOP representations yield fewer product terms than GRM expressions.

The testable realization techniques of logic functions can be used for circuit design to reduce the complexity of test pattern generation. The circuit testable realizations of multiple-valued logic functions are investigated in this paper. The multiplication modulo gates and addition modulo gates are used in the testable realization. It is shown that n+2 test vectors are sufficient to detect the Min and Max bridging faults in the testable realizations, where n is the number of input variables of multiple-valued functions. The delay in circuit can be decreased if the tree structure is employed instead of cascade structure. It is indicated that for the tree structure realizations with m-valued logic, the number of single fault test vectors is three if m-2 extra inputs and an addition modulo gate are added. Furthermore, the multiple faults detection approach of the circuit realizations is investigated, a multiple faults test set is given.

The multilevel test allows the complete testing for a circuit from the upper functional levels to the actual defective components. An approach for fault diagnosis of digital systems at hierarchical levels is presented, which employs bus observation technique and fuzzy neural networks to solve the acquirements of test information. It is shown that fault diagnosis can be done at any desired level by means of the analysis for fault information relativity and the testability of faults. The approach has been applied in a fault diagnosis system for a microcomputer; the experimental results show the effectiveness of the approach.