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Security is increasingly widespread in many embedded devices. As technology scales, fault attacks are seen as becoming more relevant to many embedded devices, revealing secrets utilized within the silicon. Despite numerous publications in fault injection, laser fault injection methodologies remain diverse with limited details on equipment and setups. A new laser fault injection methodology is proposed which combines quiescent photon emissions with backside dynamic laser pulse profiling in time and space. Empirical results illustrate the impact of the laser on multiple-instruction fault injections, and controlled instruction replacement faults. Unlike previous research, quiescent photon emissions combined with laser fault injection provides fine tuning of faulty instructions in addition to reverse engineering within each clock cycle. This research is critical for understanding how to design more secure and trustworthy hardware, including countermeasures to thwart attacks.

A wide-band lumped element model for a through silicon via (TSV) is proposed based on electromagnetic simulations. Closed form expressions for the TSV parasitics based on the dimensional analysis method are introduced. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed TSV model are fitted to the simulated S-parameters up to 10 GHz with an error less than 5%. It is shown that a TSV capacitance is highly dependent on the positions of ground contacts and has a value of tens of femto farads in a typical current technology. This value is much higher than a minimum device capacitance and requires special design methodologies such as cascaded buffers. Coupling between TSVs will be handled in another paper.

Through Silicon Via (TSV) technology is one of the most critical and enabling technologies for 3-D integration. Compared with conventional I/O structures, such as flip-chips, metal bumps, and wire-bonding, TSV technologies result in reduction of interconnect length, wire parasitics, propagation delay, and power consumption. Therefore, a compact model for a TSV is proposed based on electromagnetic simulations. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed wide-band TSV model are fitted to the simulated S-parameters up to 100 GHz with an error less than 5%.