Compact TSV modeling for low power application

Through Silicon Via (TSV) technology is one of the most critical and enabling technologies for 3-D integration. Compared with conventional I/O structures, such as flip-chips, metal bumps, and wire-bonding, TSV technologies result in reduction of interconnect length, wire parasitics, propagation delay, and power consumption. Therefore, a compact model for a TSV is proposed based on electromagnetic simulations. The proposed model enables direct extraction of the TSV resistance, self-inductance, oxide capacitance, and parasitic elements due to the finite substrate resistivity. The model's compactness and compatibility with SPICE simulations allows the fast investigation of a TSV impact on a 3-D circuit performance. The parameters' values of the proposed wide-band TSV model are fitted to the simulated S-parameters up to 100 GHz with an error less than 5%.