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In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.

Multi-threshold null convention logic (MTNCL) is a novel low power paradigm for designing asynchronous null convention logic (NCL) circuits. To further reduce the dynamic power consumption, a new methodology that utilizes gate diffusion input technique is proposed. The proposed approach is used to realize MTNCL gates and a decrease in the transistor count is observed that tend to reduce the dynamic power consumption. Compared to SMTNCL approach, the proposed methodology shows a 5.6% is reduction in the power consumption for the MTNCL gates.

Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

The increasing power consumption in the synchronous circuits is the major concern in the semiconductor industry. The major contributor to this power consumption is the clock generator and the clock distribution. This problem can be addressed by using the asynchronous circuits. Null Convention Logic (NCL) is one of the most commonly known delay insensitive approach for designing asynchronous designs. However, realizing the NCL circuits using the commonly used complementary metal oxide semiconductor (CMOS) technique is said to increase the area and the power consumption. The low power design technique known as Gate Diffusion Input (GDI) can be used for implementing the NCL circuits to reduce both the area and the power. Application of the external input to the sources of the pMOS and nMOS transistors, allows to reduces the area and the dynamic switching. Thus, decreasing the transistor count and the power. The proposed GDI NCL technique is used for designing the 4-bit un-pipelined NCL multiplier. The design was realized and simulated in gpdk045 Cadence Virtuoso. In comparison to the CMOS model, the GDI model shows 21.6 % in transistor count and the dynamic power is reduced by 13.7 %.

Null Convention Logic (NCL) is the one of the well-known clock-less approaches for designing asynchronous logic circuits. The complementary metal oxide semiconductor (CMOS) technology is usually used for implementing the NCL circuits, which as a major drawback of large area consumption and power dissipation. These limitations have been addressed by adopting a low-power design technique called Gate Diffusion Input (GDI) in this work. GDI technique allows implementing primitive logic gates using only two transistors. Thus, it not only reduces the transistor count but also the power consumption. However, GDI technique suffers a significant voltage drop across the circuit, due to its inherent voltage swings. Thus, to ensure full swing output regenerative buffers are added at the output stage which tends to increase the overall latency. In this work, a novel GDI and HYBRID (CMOS+GDI) designs are proposed to overcome the limitations of the CMOS-NCL designs. The proposed approaches were tested by realizing NCL Ripple Carry Adder (RCA). The proposed model was simulated in Cadence Virtuoso and power reduction of 14.9 % and 9.8 % has been observedfor GDI and HYBRID models, respectively.

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.

Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method"s accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

This article describes a novel technique for analysing the effects of supply voltage noise on circuit delay for VLSI circuits. Scattering parameters are used to model the supply voltage variation in the frequency domain and to reduce the original power grid and simulation time. The interconnections of the power grid are modelled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOSFET modelling method for a static timing analyser is proposed based on the power grid analysis. A MOSFET logic is modelled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimisation problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45 nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results.

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-V th-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of V DD and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

This paper presents a novel statistical characterization for accurate timing and a new probabilistic-based analysis for estimating the leakage power in partially depleted silicon-on-insulator (PD-SOI) circuits in 100-nm BSIMSOI3.2 technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI complementary metal-oxide-semiconductor (CMOS) circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fan-out effect, along with a new input-independent method for estimating the leakage power based on a probabilistic approach. The proposed timing and leakage power estimate algorithms are implemented in MATLAB, HSPICE, and C. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5%, compared with random simulation results.

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4×4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.

In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.

This paper presents a CMOS neuron circuit design based on the Hindermarsh-Rose (HR) neuron model. In order to be fabricated in a 0.18㎛ CMOS technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This on chip solution also minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. Simulation results demonstrate that the proposed CMOS neuron performs the expected waveform with time and amplitude scaled. The chip was fabricated by MagnaChip with an active die area of 1.1㎟ including I/O pads. The experimental results validate the performance of this CMOS neuron.

As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown (also called time dependent dielectric breakdown (TDDB)) has become a major reliability concern. The oxide breakdown is categorized into hard breakdown (HBD) and soft breakdown (SBD). With the present of HBD and SBD, it is difficult to control the ON current of the MOSFET device. Especially, HBD causes a catastrophic failure of the device and the entire circuits. In this paper, the TDDB effects on the delay and power of the nanoscale CMOS circuits are analyzed using ISCAS85 benchmark circuits, which are designed using a 45-nm CMOS predictive technology model. Based on the TDDB analysis, a new hard breakdown monitoring circuit has been proposed.

This paper proposes on-chip process and temperature sensor circuits to find a minimum data retention voltage in nanoscale CMOS systems. The process variation is monitored by the low cost gate tunneling leakage sensor, and the temperature is monitored using a zero temperature coefficient (ZTC) principle. The minimum data-retention voltage of flip-flops for low power operation is generated for different temperature and process corner conditions adaptively using a look-up-table method based on the simple PT monitoring circuits. The proposed circuits are implemented using 45 nm CMOS predictive technology model.

As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown, also called time dependent dielectric breakdown (TDDB), has become a major reliability concern. With the present of TDDB, it is difficult to control the ON current of the MOSFET device. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the TDDB effects on delay and power of the nanoscale CMOS circuits are analyzed using inverter chains and ISCAS85 benchmark circuits, which are designed using 45-nm CMOS predictive technology model. Finally, we discuss post-silicon adaptive tuning techniques to compensate the TDDB impact on the CMOS circuits.

Skin sensor is the most critical part for controlling robot sensing behavior. In this paper, we provide circuit implementation and simulation for sensing the pressure in the skin sensor using CMOS and CNFET at 32nm technology node. The proposed scheme can be used as an active matrix like memory element in the skin sensor and it is demonstrated by showing the output image according to the skin sensor's pressure location using Matlab implementation. The circuits are compared with CMOS and CNFET (Carbon Nanotube FET) at different supply voltages to show the feasibility of the scheme. Also, low-leakage circuit technique is applied to the proposed sensing circuit.

The demand for power sensitive designs in system-on-chip (SoC) has grown significantly as MOSFET transistors scale down. Since portable battery powered devices such as cell phones, PDA’s, and portable computers are becoming more complex and prevalent, the demand for increased battery life will require designers to seek out new technologies and circuit techniques to maintain high performance and long operational lifetimes. As process dimensions shrink further toward nanometer technology, traditional methods of dynamic power reduction are becoming less effective due to the increased impact of standby power. Therefore, this paper proposes a novel adaptive power management system for nanoscale SoC design that reduces standby power dissipation. The proposed design method reduces the leakage power at least by 500 times for ISCAS’85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

This paper proposes a new hybrid MOSFET /carbon nanotube FET (CNFET) power gating structure using 32nm technology at a low voltage (0.6V). The power gating structure is one of the most effective methods to reduce the power dissipation of systems in sleep mode, but it suffers from increased propagation delay due to the high threshold voltage of power switches in the low voltage region. In this paper, to reduce the propagation delay of the power gating structure while keeping low leakage power in the sleep mode, the CNFETs are deployed as a power switch. This hybrid structure reduces the time gap in switching over from silicon MOSFET to CNFET technology. For a trade-off between wake-up overhead and leakage power saving, a four-power-mode PG structure using back-gate biasing of the CNFET switches is also proposed. The simulation results are compared to those of the MOSFET power gating designed 32nm technology.

A novel power gating (PG) structure using series-connected low-V th power switches has been developed to extend the PG structure to the ultra-low voltage region while keeping low leakage power in sleep mode. The series-connected low-V th power switches induce a short wake-up time due to fast current discharge through the switches, whereas the PG structure can suffer from large gate tunneling leakage currents and wake-up rush-currents. Therefore, in this paper, extra circuitries are added to control the gate-tunneling leakage and rush-currents; however the total PG switch size of the proposed PG structure including the extra circuits is the same as the conventional one. The simulation results are compared to those of other well-known PG schemes and show that, in the ultra-low voltage region, the other high-V th based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6V supply voltage which are designed using 45nm CMOS predictive technology model.

This paper proposes a new design of carbon nanotube FETs (CNFETs) based SRAM cell operating in subthreshold region. By using optimum back-gate biasing scheme for each transistor, the proposed SRAM cell achieves the best overall performance considering noise margin, delay and power. Compared with traditional subthreshold CNFET SRAM cell, the proposed SRAM cell increases static voltage noise margin (SVNM) 36%, increases static current noise margin (SINM) 2.5X, and reduces delay 61% with power consumption increasing only 1% for read operation. For write operation, the proposed SRAM cell increases write noise margin (WNM) 2.5X and reduces power consumption and delay 17% and 56% respectively compared with traditional subthreshold CNFET SRAM cell. In terms of total number of nanotubes (area) of CNFET SRAM cell, the proposed subthreshold CNFET SRAM cell can reduce at least half of total number of nanotubes without compromising noise margin, power and delay. New CNFET SRAM cell structure is proposed to dynamically bias each transistor at different operation modes.

This paper presents the hot-carrier-injection (HCI)-induced delay degradation of the power gating structure as well as the HCI impact on critical issues in the power gating, such as leakage power, wake-up time, and wake-up rush-current. Considering this HCI impact, a novel adaptive HCI-aware power gating structure is proposed to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the HCI effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new HCI monitoring circuit, which is imperative for a good adaptive technique. The simulation results are compared to those of power gating without the adaptive technique and show that both the circuit-delay and wake-up time dependence of the power gating structure on the HCI stress is minimized with only 2% and 3% increase, respectively while keeping small leakage power and rush-current. The proposed technique is evaluated using ISCAS85 benchmark circuits which are designed using 45nm CMOS predictive technology model.

This paper presents a novel probability based analysis for leakage power estimation of partially-depleted silicon-on-insulator (PD-SOI) circuits. The proposed leakage power estimation algorithms is implemented in C language, and the proposed methodology is tested by ISCAS85 benchmark circuits designed in 100 nm SOI technology. The results show that the error is within 4% compared with Hspice Monte Carlo simulation results.

This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, the control system determines the optimal trade-off between supply voltage and the forward body bias voltage to satisfy the performance requirement. In the standby mode, a new optimal body-bias technique in nanoscale CMOS technology is implemented to monitor subthreshold, gate tunneling, and band-to-band tunneling leakage current and reduce leakage current by optimal substrate bias voltage(forward of reverse biasing). The optimal body bias control system reduces the leakage current by up to 1000 times for ISCAS85 benchmark circuits designed using 32nm CMOS technology

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.

This paper presents a novel statistical characterization methodology for accurate timing analysis for Partially Depleted Silicon-On-Insulator (PD-SOI) digital circuits. The proposed methodology is applied to ISCAS85 benchmarks circuits, and the results show that the error is within 5% comparing to HSpice simulation results.

A method for estimating power consumption of digital CMOS VLSI chips is developed. The method estimates the total power consumption of a chip by analyzing separately for different parts of the chip, which are logic circuit, on chip memory, interconnection, clock distribution, and off chip driving. This method makes it possible to estimate the power consumption of a digital CMOS VLSI chip based on gate count, memory size, and logic circuit. An estimation tool, which is implemented in C language, is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions