Search

Archives of electrical engineering 69(1), 187-202 (2020). doi:10.24425/AEE.2020.131767, Published by Versita, Warsaw

An in-depth analysis on the load transient operation of a buck converter with auxiliary current control is presented in this article. The analysis quantifies the effects of nonideal characteristics, such as the equivalent series resistance, inductor current and output voltage ripples, time delay, and slew rate of the load current, on the fluctuation of the output voltage in a practical implementation. The analysis results reveals that some of the non-idealities may cancel each other out and become negligible in the implementation. A design considering the nonidealities can achieve the transient-wise capacitor charge balance of the output capacitor and minimize the output voltage deviation during the load transient. The agreement between the simulation and experimental results validates the effectiveness and precision of the proposed analysis and design.

In this article, a new nonisolated full soft-switching step-up dc/dc converter is introduced with a continuous input current for renewable energy applications. The use of a three-winding coupled-inductor (TWCI) along with a voltage multiplier, enables the proposed converter to enhance the voltage gain with lower turns ratios and duty cycles. Also, a lossless regenerative passive clamp circuit is employed to limit the voltage stress across the power switch. In addition to zero current switching performance at the turn- on instant of the power switch, the turn- off current value is also alleviated by adopting a quasi-resonance operation between the leakage inductor of the TWCI and middle capacitors. Moreover, the current of all diodes reaches zero with a slow slew rate, which leads to the elimination of the reverse recovery problem in the converter. Soft-switching of the power switch and all the diodes in the proposed converter significantly reduces the switching power dissipations. Therefore, the presented converter can provide a high voltage gain ratio with high efficiency. Steady-state analysis, comprehensive comparisons with other related converters, and design considerations are discussed in detail. Finally, a 160 W prototype with 200 V output voltage is demonstrated to justify the theoretical analysis.

A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The design...

Objectives: To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. Methods: OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. Findings: The proposed Biquad filter improves the frequency response, power dissipation and provides vary of the KHN biquadratic filter circuits it uses minimum numbers of Operational Transconductance phenomenon Amplifier (OTA) to realize an equivalent. The assorted parameters specifically Center frequency, dcgain, Bandwidth, Power Dissipation and Quality issue are all electronically tunable. OTA based Biquad filter is simulated in CADENCE Virtuoso tool. Opamp-RC Biquad filter offers a bandwidth of 425 kHz, pass band gain of zero DB, whereas Gm-C measuring system based mostly filter offers 85MHz, passband gain of zero DB. Over-all power dissipation of the Biquad filter is 4.3mW with 1.8V DC Supply has basing current of 50mA with gracefully voltage 2.5v. by keeping the supply voltage, bias current and load capacitor as 2.5V, 50mA and 10pFrespectively, it has been seen that the power is reduced using the CADENCE virtuoso tool. Novelty : This study presents a Universal Biquadratic filter having less power dissipation. The circuit was optimized for gain, GBP, slew rate, areas, voltage offset, phase margin, power area etc. compared to all the previous filter circuits (OTA GMC filters, OTA type-C filters) designed with the help of OTA. Keywords: OTA; CMOS; CADENCE Virtuoso; Static Power; Dynamic Power; MOSFET

A study of the reset transient of charge-sensitive amplifiers operating with a pulsed switch in parallel to the feedback capacitance is presented. Analytical models have been developed for amplifiers in both linear and slew rate regimes during the reset phase. The models predict the time interval required to reset the amplifier that, in most cases, significantly differs by the simple discharge of the feedback capacitance through the switch resistance and strongly depends on the open-loop gain and bandwidth of the core amplifier and on the input capacitance. The models also quantitatively predict spurious voltage transients at the preamplifier’s input and possible ringings at the output, as a function of the main general parameters of the circuit. A case application study of the presented model is proposed for low-capacitance detectors, such as semiconductor drift detectors or small pixel detectors.

In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (D...

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 $\mu \text{m}$ HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of $\text{d}{V} _{\mathrm {SSF}}$ /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM1 and FoM2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

Ever since the reliability issues caused by I/O (input/output) compatibility among chips fabricated using different processes were raised during mid-2000, on-silicon mixed-voltage I/O buffer with wide voltage tolerance has been considered a better solution than using signal level converters to shrink PCB size, number of discretes, and power consumption. However, various external voltages on I/O pad result in body effect, leakage, hot-carrier degradation, and gate-oxide overstress in stacked transistors of mixed-voltage I/O. What even worse is that slew rate (SR) was also found deteriorated by PVT (Process, Voltage, Temperature) variations. A complete mixed-voltage I/O buffer design flow using nano-scale CMOS processes will be introduced in this tutorial based on previously developed buffers. Besides circuit design methodology, the reliability design consideration for the buffers, including ESD, PVT detection, and slew rate auto-adjustment will be discussed as well.

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a −3dB bandwidth in the range 0.1–212 Hz. Moreover, the amplifier is designed in 0.18- $\mu \text{m}$ CMOS process and the chip area of the proposed circuit with pads is $450\times 450\,\,\mu \text{m}^{2}$ . The adjustable LPF has a 100 Hz cut-off frequency. The proposed circuit has an input-referred noise of $0.7~\mu $ Vrms, (0.1 ~ 100Hz) and a power consumption of 380 nW at 1 V supply.

This work proposed a binary-weighted Digital-to-Analog Converter (DAC), which is designed to be used in Asynchronous successive approximation register (SAR) based Analog-to-digital converters (ADCs) specifically and in other relevant operations .The design has yielded an improved slew rate, and it is less prone to noise as the size of capacitors is taken in accordance with KT/C noise calculation. For achieving all mentioned goals, and to restrict the size of DAC, within suitable dimensions charge scaling DACs are used. One more advantage of this design is its accuracy, further it does not require op-Amps for its operation. Results of statistical simulation and mathematical consideration are published which depicts the supremacy of the design. A high-resolution DAC designed for this specific purpose has to have special consideration for the effect of local mismatch, parasitic and matching of the capacitors, for that, the common-centroid approach has been followed. This design has displayed a high resolution with small unit capacitances and that too without expensive factory calibration.

This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stability degradation, using a rail-to-rail controlled feed-forward path used in parallel with the main ring amplifier. It offers additional degrees of freedom to improve the linearity/power consumption trade-off proposed in other reported slew-rate enhancement techniques. The proposed design has been implemented and simulated in a low-cost CMOS 65 nm technology. Operating from a single 0.9 V power supply, it consumes $186~\mu \text{A}$ for switching frequency of 210MHz. For the same current consumption, it achieves an improvement of 10 dB in the total harmonic distortion (THD) compared to state-of-the-art.

Ultrafast and isolated gate drivers advance the development of pulse and very high frequency power electronics for applications that include LiDAR, space systems, miniaturized hardware, and testing of emerging ultrafast devices. The isolated ultrafast gate driver in this letter achieves a gate voltage slew rate above 12 GV/s with rise and fall times below 260 ps with the proper choice of components. Magnetic isolation provides transient immunity and positive feedback enables dynamic dc restoration to allow arbitrarily long on - and off -times and preserve variable duty cycles. With the isolated ultrafast gate driver, an EPC 2038 GaN FET achieves a drain voltage slew rate of over 37 GV/s when hard-switching and improves total efficiency by 8% (including gating loss) with a careful choice of logic inverters in a symmetric 100 MHz current-mode class D (CMCD) wireless power transfer system. The ultrafast gate driver with isolation and positive feedback was implemented with a commercial radio frequency signal transformer and discrete logic inverters and validated in a hard-switching double pulse test, a narrow pulse test repeating at 165 MHz, and a 100 MHz soft-switching CMCD resonant converter.

Since the CMOS technology moving forward swiftly, digital data exchange between chips fabricated using different generations of technologies becomes a problem when the size of printed circuit board-based systems is critical for mobile or wearable devices. To achieve better performance, smaller size, and power efficiency, a 2 $$\times $$ VDD output buffer featured with process, voltage, and temperature detection and the integration of dual-Vth and standard Vth transistors optimized by W/L sizing is proposed. Slew rate (SR) self-adjustment and power–delay product reduction are also verified by Monte Carlo simulations to achieve at least 27.8% improvement and 37.6% reduction. The prototype of this investigation fabricated by a typical 28-nm CMOS process is measured on silicon to attain at least 7.6% SR improvement.

With features such as faster switching frequency and higher breakdown voltage, wide bandgap power devices are key enablers to address the increasing demand for higher power density and higher efficiency in future medium-voltage converters. The 10-kV SiC MOSFET is one of such devices; yet, to fully utilize its benefits, a gate-drive power supply capable of meeting the necessary insulation (voltage) and isolation ( dv/dt voltage slew rate) requirements is needed. To this end, this article presents the complete design and optimization of such a power supply meeting four critical objectives: 1) high power density with high-voltage (HV) insulation; 2) minimum input–output capacitance; 3) fault ride-through capability; and 4) good voltage regulation. To this end, a GaN-based inductor-capacitor-capacitor-inductor (LCCL)- LC resonant converter switching at 1 MHz was used to produce a resonant current source and to supply multiple isolated loads (gate-drivers) through the single-turn primary winding loop. Experimental results are shown demonstrating the attained power density (6.3 W/in3), input–output capacitance (1.67 pF), peak efficiency (86.0%), short- and open-circuit fault withstanding capacity, and insulation rating (partial discharge inception voltage of 12 kV).

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

This study introduces the design of a practical three-stage operational amplifier (op-amp) using nested Miller compensation, particularly for piezoelectric actuators. Driving a piezoelectric actuator represents a challenge in amplifier design due to its large capacitive nature. A stable piezo driver needs to be free of oscillations and phase lag. Direct feedback compensation using a conventional Miller capacitor is an effective method as long as the capacitance of the load is considerably close to the value of the Miller capacitor. However, using a large capacitor causes a decrease in the slew rate and gain bandwidth. To avoid this, our design focused on the utilization of nested Miller compensation technique. A prototype of the design working at 100V peak to peak voltage (Vpp) is implemented using commercial off-the-shelf (COTS) components. The measurements show the successful driving capability and step-response of the op-amp design. In the design, Widlar current source is also utilized for thermal stability and short circuit protection. According to simulation results, the proposed op-amp has a slew rate of 0.5 V/μs, an open loop gain of 90dB with 3MHz Gain Bandwidth Product (GBP) and phase margin of 77°, and a common mode rejection ratio (CMRR) of 62dB.

A bandwidth and slew rate (SR) enhanced operational transconductance amplifier (OTA) with proposed sustainable dynamic bias, transient detector and passive on-chip high-pass filter is presented in this brief. The proposed design is able to detect large-signal applied to the input of the amplifier and dynamically adjust its bias current to enhance both unity-gain bandwidth (UGB) and SR at the same time to achieve fast-settling behavior without overshoot and undershoot, along with high immunity against variations of supply voltage and bias current. Fabricated with a commercial 130-nm CMOS technology, the proposed design is verified by measurements that it is able to increase its SR by over 15 times, with more than 7.5 times reduction in its power consumption to attain fast settling time compared with a conventional design. Design considerations and an architectural comparison of the proposed design with another design with a different approach are also included in this brief to verify its performance and viability.

In this work, a fast and low-power sigma delta ∑ Δ analogue-to-digital converter (ADC) has been developed using a hetero-material electrically-doped nano-wire tunnel field effect transistor (HM-ED-NW-TFET) for the first time. The better gate controllability of nano-wire and immunity against process variations of electrically doped tunnel field effect transistor (TFET) enhances resolution. In this regard, the first step that has been performed is the material engineering using A l x G a 1 − x Sb / GaA s 1 − y P y , to achieve significant driving current at low subthreshold swing and high I ON / I OFF ratio. Secondly, the mole fraction is optimised to upgrade the critical analogue component – the op-amp. Also, drain under lapping is included in p-TFET to bring its characteristics as close to n-TFET. Latter, the look-up tables of the proposed device has been generated which is used to develop individual block of ∑ Δ ADC in Cadence. The blocks are well verified and integrated into final ∑ Δ ADC and its performance is evaluated. Hence, this work has explored the inherent merits of HM-ED-NW-TFET in the development of low power and fast ∑ Δ ADC by virtue of a high slew rate op-amp. Therefore, this work contributes a novel approach to explore the characteristics of emerging devices in mixed signal applications.

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

This paper presents the design and implementation of a high-frequency/very high frequency (VHF) multiresonant gate drive circuit. The design procedure outlined here is greatly simplified compared with other VHF self-oscillating multiresonant gate drivers presented in previous works. The proposed circuit can reduce the long start-up time required in a self-oscillating resonant gate drive circuit and utilize the fast transient capability of VHF converters better. We demonstrate a prototype resonant gate driver, which reduces up to 60% of the gate-driving power in a 20-MHz 32-W Class-E power amplifier using a Si MOSFET. The proposed technique could also drive a high-voltage rated SiC MOSFET at 30 MHz with a slew rate of 2.5 V/ns at the gate, while an integrated hard-switching gate driver only provides a slew rate of 1.8-V/ns and is five times less efficient than the proposed resonant gate driver.

This article presents a class-AB operational transconductance amplifier (OTA) with a high slew rate. The proposed class-AB OTA is applied with a slew-rate enhancement technique using an extremely low quiescent current. The additional current-reference common-mode feedback loop resolves the susceptibility to process, voltage, and temperature fluctuations resulting from slew-rate enhancement transistors. The proposed class-AB OTA is most widely used in block design, including, a switched-capacitor circuit, analog-to-digital converter, digital-to-analog converter, low-dropout regulator, and switched-capacitor DC-DC converters. In this study, performance was validated by applying the proposed class-AB OTA to a switched-capacitor delta-sigma modulator which requires high performance and high precision. The circuit was designed and simulated using a 0.18- $\mu \text{m}$ complementary metal-oxide semiconductor process.

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

The flipped-voltage-follower-based low-dropout regulator (LDO) has drawn attention for its fast response and reduced complexity, while super source follower can be combined to push the pole at the gate of the pass device to high frequency. But the maximum load current and minimum load capacitance of this topology are limited, especially when the poles and zero from the SSF are omitted in previous designs. This paper proposes a solution to extend the ranges of the load current and load capacitance, by implementing a small feed-forward capacitor ( $C_{F}$ ) and a damping factor control circuitry. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot. The proposed LDO is verified in a 65-nm CMOS process with 0.008 mm2 active area. The measured voltage undershoot is 80 mV with a load steps from 100 μ A to 50 mA with 2-ns edge times, with no external capacitor. And the maximum load capacitance can be extended to 2 nF. A figure-of-merit of 0.8 mV is achieved.

Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However,insights in design choices such as power optimization are still missing for such systems. Here wediscuss system level choices with the help of a simple model. Using precise electrical simulations,we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in astandard 180-nm CMOS technology

The influences of on-resistances and parasitic elements on the static current sharing of N-paralleled discrete silicon carbide (SiC) MOSFETs are analyzed in this paper. First of all, the limitation of self-balancing effect of MOSFETs caused by the positive temperature dependent on-resistance is quantitatively analyzed. From a statistical analysis, the current sharing distribution according to the spread of on-resistances is presented, which helps to screen the proper devices based on the current sharing requirement. Furthermore, a general circuit model is proposed to analyze the effect of inevitable circuit parasitic elements on current sharing with a given current slew rate. With the recursive circuit model, current imbalance contributed by parasitic resistances and inductances can be separately calculated, which can be used to guide the hardware design to improve current sharing in a real converter. The theoretical analysis is verified by experimental results.

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

In this paper, a 0.5 volt, two-stage, pseudo-differential, high gain, and rail-to-rail bulk-driven operational transconductance amplifier (OTA) is presented. At the input stage, a new common-mode feedback method based on the cross-coupled structure is adopted with an output conductance stabilization circuit to overcome the gain variation brought by this new solution. At the output stage, a novel class-AB output circuit is proposed which makes full use of bulk terminals. This OTA is designed in 180nm CMOS technology. The DC gain and unit gain bandwidth are 71 dB and 5.7 MHz, respectively with phase margin of 51° under a capacitive load of 20 pF at the normal case. The average slew rate is 3.55 V/µs. Other simulation results also presented in detail which validates the proposed solution.

A high accuracy, low distortion circuit technique is proposed to reduce the power consumption in switched capacitor circuits. The technique uses passive charge compensation for slew enhancement and correlated level shifting (CLS) to reduce the output swing for greatly improved linearity in switched capacitor integrators. The proposed technique is verified by implementing it in a single-bit discrete-time second-order delta sigma modulator. Simulation results show the SNDR is improved by 9 dB compared to the conventional architecture.

International audience; This paper evaluates the performance of two on-chip sample & hold (S&H) voltage sensors, usable for power integrity measurements, with the aim to compare silicon-on-insulator (SOI) & bulk CMOS technologies. Both sensors were designed and simulated in 180 nm 5 V AMS-bulk and XFAB-SOI processes, using optimized parameters and compatible devices. The fundamental variables analyzed were power consumption, leakage current, slew rate (SR), and transient output voltage, under process, voltage and temperature variations. Compared to bulk technology, SOI was found to have lower power consumption (by 2.2 mW in average) and leakage supply current (by 9.5 pA at 27 ○ C), higher sensitivity to process variations (up to 88% additional slew rate versus 39% at 80 ○ C), higher resilience to temperature changes (6% in output voltage), and a larger occupied area. The SOI sensor is intended to be fabricated and used to evaluate injected continuous wave and transient disturbances as well as voltage fluctuations due to internal activity on power distribution networks.

Due to the commercial use of battery-powered portable devices, low power circuits are required. A low power, low noise front end is the important key for various battery-operated devices for real-world applications. In this review paper, various modifications of popular front-end with their performance parameters like CMRR, PSRR, slew rate, power dissipation, etc. have been studied. The comparison between different topologies of front-end amplifiers to have more power-efficient, low noise, high gain, and better bandwidth at low supply voltages to be analyzed. This review paper provides an assessment of low power front end amplifiers.

Advances in wide-bandgap devices have enabled increased switching frequencies in modern power converters. As a result, the parasitic inductance arising from switching cell layout has become critical to converter performance and operation. This inductance not only reduces slew rate, which degrades efficiency, but can also cause electromagnetic interference and destructive voltage overshoot. This paper presents a method for estimating the inductance of printed circuit board (PCB) commutation loops, targeted for rapid iteration by the power electronics designer. Based on partial inductances, the computationally efficient approach is amenable to fast parametric sweeps. The proposed technique is also platform-independent, such that it may be scripted into existing optimization tools. To validate the accuracy of the technique, a detailed quantitative comparison is performed with commercial simulation tools as well as experimental measurements on a number of hardware prototypes.

Over the last few decades, low power design has become unease in VLSI design, particularly for movable and high performance systems. Power dissipation is crucial for deep sub – micron technologies. There is a need for efficient leakage diminution techniques to minimize MOS leakage currents. Reduced leakage currents extend the life of all battery operated devices like mobiles, laptops. To reduce the power dissipation in digital VLSI design, we use different types of techniques. Compared to bipolar technology, CMOS technology provides low power dissipation. But, still this topology suffers with high leakage and dynamic power consumption. These hiccups can be overcome by making use of multi-threshold and asynchronous methodologies into the conventional CMOS technology. In this paper, we investigate the performance of various threshold templates and combinational circuits using various low power and asynchronous topologies. Latest topologies like Multi Threshold CMOS (MTNCL) and Multi Threshold Null Convention Logic (MTNCL) are compared with existing CMOS technology in terms of constrains like power dissipation, delay, slew rate and energy performance.

A single-stage multipath class-AB bulk-driven operational transconductance amplifier working in weak inversion region with enhanced power efficiency is presented in this paper. The proposed bulk-driven amplifier makes use of four signal path to conduct small signal current, which leads to significant enhancement of transconductance when compared to conventional recycling structure. In addition, two of the signal paths build output stage operating at class-AB, resulting in a boost of slew rate. Most of all, the power efficiency of the proposed amplifier is improved over that of traditional recycling counterpart, enabling it more suitable for low-power applications. Simulated on SMIC 180 nm process, results demonstrate that the proposed bulk-driven amplifier achieves a 256% slew rate improvement and 100% unity-gain bandwidth enhancement when compared to the conventional recycling structure.

This paper describes a bandwidth (BW)- and slew rate (SR)-enhanced class AB voltage follower (VF). A thorough small signal analysis of the proposed and a state-of-the-art AB-enhanced VF is presented to compare their performance. The proposed circuit has 50-MHz BW, 19.5-V/ $\mu \text{s}$ SR, and a BW figure of merit of 41.6 (MHz $\times $ pF/ $\mu \text{W}$ ) for $C_{L} = 50$ pF. It provides 13 times higher current efficiency and 15 times higher BW than the conventional VF with equal 60- $\mu \text{W}$ static power dissipation. The experimental and simulation results of a fabricated test chip in the 130-nm CMOS technology validate the proposed circuit.

This paper presents two methods to reduce power consumption of switched capacitor (SC) integrators in sigma-delta analog to digital converters. The proposed two methods are based on the passive charge re-distribution technique, injecting charge into the output of the first integrator. The injected charge can be attained by a continuous function of the input voltage and feedback, or by quantizing the injected charge into three levels. In both cases, the main purpose is to minimize the initial transient voltage at the input of the first operational transconductance amplifiers (OTA), in order to bypass the slewing region of the OTA and enter into the linear settling region. Then a minor charge is left, and needs to be moved by the OTA. Using these two charge pumping techniques separately, a 10-bit performance of a conventional second-order delayed cascaded 1-bit sigma-delta modulator which consists of two SC integrators can be obtained by only consuming 60% power dissipation of the traditional structure without proposed techniques.

This paper presents a new technique to improve CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp). Our modification is based on shorting two nodes in the conventional RFC circuit. It causes that the seen resistance from the created new node be half of the conventional RFC counterpart and makes it to double the slew rate. Compared to it, our circuit is also capable to enhance DC gain and unity gain bandwidth (UGBW) with increasing output resistance of differential pair. Moreover, our proposed improvements are in better fast-settling time, input referred noise, input offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) in the same power consumption. Simulation results in 180 nm CMOS process indicates that the proposed amplifier has 1.5 times the unity gain bandwidth (185 MHz versus 125 MHz) and also has 7 times gain boosting (75 dB versus 58 dB) with better figure of merit (FOM) in the same power consumption, driving capacitor load of 10 pF @1.2 V power supply. The results also demonstrate that the temperature sensitivity, power supply variations and process corners have a negligible effect on the proposed amplifier stability.

This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .

Comparators are very important and essential circuits in the implementation of analog to digital converter (ADC) architectures. In this work, three different types of CMOS comparator architectures ...

As semiconductor technologies have been shrinking, the speed of circuits, integration density, and the number of I/O interfaces have been significantly increasing. As a consequence, electromagnetic emanation (EME) becomes a critical issue in digital system designs. Electronic devices must meet electromagnetic compatibility (EMC) requirements to ensure that they operate properly, and safely without interference. I/O buffers consume high currents when they operate. The bonding wires, and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference (EMI). Therefore, I/O switching activities significantly contribute to the EMI. In this paper, we evaluate and analyze the impact of I/O switching activities on the EME. We will change the circuit configurations such as the supply voltage for I/O banks, their switching frequency, driving current, and slew rate. Additionally, a trade-off between the switching frequencies and the number of simultaneous switching outputs (SSOs) is also considered in terms of EME. Moreover, we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns. The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations. All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

This paper presents a new passive-active ΔΣ modulator with high-resolution and low-power applications. An open-loop unity gain buffer is used to improve the performance of a passive switch capacitor integrator. Since this technique compensates phase and gain errors, there is no need for large capacitors, which result in a great reduction in the chip footprint. The first filter is passive, so the output swing of the amplifier is small but large enough to guarantee the linearity and a relaxed slew rate in the modulator structure, which leads to the low power. Using the second-order modulator with an adequate oversampling ratio leads to the desired SNR. The post-layout simulation of the second-order passive-active modulator is performed in Spectre/Cadence electrical simulator using TSMC 0.18 CMOS model in the standard 0.18 μm CMOS process. The dynamic range of 92.4 dB, peak signal to noise ratio of 88.6 dB, peak signal to noise plus distortions of 82.7 dB were achieved while consuming 1.93 μw in a 500 Hz signal bandwidth at 1.5 V supply, giving a FoM Walden of 0.173 pJ/ conv-step and the FoM Schreier is 176.53 dB.

Buffer devices and voltage scalers are widely used in various analog-digital systems, when it is necessary to match the signal in the form of voltage from a low-power sensor to a load, it consumes significantly more power. In this case, the voltage buffer is characterized by a voltage transfer coefficient close to unity, and must also have a high input resistance and sufficient load capacity. The voltage scaler, in contrast to voltage buffers, must additionally provide the necessary gain transfer ratio, which can be substantially more than one. The circuit design features of three variants of the construction of voltage buffer cores and voltage scaling are considered. It is proved that it is advisable to reduce the input zero bias current by using amplifying n-p-n and p-n-p transistors, as well as Shiclay transistors in the input stages. The static and dynamic characteristics of the voltage buffers and the voltage scaler must meet the system requirements of the device. The static characteristics should be attributed primarily to the error of the transfer characteristics of the scale, zero offset and linearity. The dynamics of these devices is determined by the frequency response and transient response. Static and dynamic characteristics are analyzed by computer simulation where it is shown that the scale errors of the voltage buffers and the voltage scaler do not exceed 10 µV in the range of the corresponding signal ± 5 V, and the linearity errors are 300 nV. A transient response was obtained which states that the slew rate of the output voltage will be no worse than 2000 V/µs. A comparison of the metrological characteristics of the voltage buffers and the voltage scaler in the form of a set of cores and output push-pull DC amplifiers. It is proved that the use of these amplifiers allows significantly (by 3-4 orders of magnitude) to improve the load capacity of the circuits while maintaining the level of the input zero bias current, as well as scale and linearity errors.

The active control of the current slew rate of hard switched voltage source inverters is a common method to reduce the electromagnetic emissions, overshoot and ringing. In a previous work, the authors derived a model-based optimal slew rate control strategy which combines iterative learning control (ILC) with an adaptive feedforward control for a single half-bridge inverter. This control strategy minimizes the switching losses while the current slew rate stays within desired limits. This paper presents the required extensions of the current slew rate control strategy for a three-phase voltage source inverter driving a permanent magnet synchronous machine (PMSM). The extended control strategy is implemented on a rapid prototype test bench to verify the performance by a number of measurement results. The results show that the current slew rate of each phase is controlled separately within the defined limits while the switching losses are minimized, independent of the load current, the supply voltage and the temperature.

A $2{\boldsymbol \times }$ VDD I/O buffer based on deterministic PVT variation detection algorithms to achieve slew rate compensation is proposed in this brief. By using the P-PVT and N-PVT Variation Detectors consisting of an inverter and a capacitor, the slew rate variation is significantly reduced against the PVT variation. Besides, the source-drain leakage current is reduced by turning off the auxiliary current paths after the charging and discharging transients are completed. The proposed design is implemented using a typical 40-nm CMOS process. The area of the I/O buffer is $0.216 {\times } 0.052$ mm $^{2}$ . Based on post-layout simulations, the slew rate variation is reduced 38.29% after the process, voltage, temperature, and leakage compensation in the worst case.

In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplifier followed by a class-B amplifier. The functionality of the class-B transconductance amplifier is dictated by a predefined hysteresis, and operates in parallel with the main amplifier. The proposed solution demands small static power (under 20% of main amplifier power) due to its class-B nature. The experimental results in a 40-nm CMOS technology show more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters. Compared with the core amplifier, HD3 at 500 MHz reduces by more than 10 dB when the SR boosting circuit is activated.

This paper presents a fully on-chip mixed-mode low-dropout (LDO) regulator with improved regulation and transient responses. With the help of the digital regulation part, the supported maximum load current is significantly improved, while the chip area overhead is very small. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. A proof-of-concept LDO design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V, and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA, which is more than 480% improved over the traditional design without digital assistance.

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, ${C} _{L}$ . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable ${C} _{L}$ . The OTA is fabricated in a standard 0.35- ${\mu }\text{m}$ technology and occupies 0.0027 mm2 of die area. Under 1.4-V supply and 6.36- ${\mu }\text{A}$ quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any ${C} _{L}$ larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.