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Your search keyword '"Richardeau, Frédéric"' showing total 6 results
Start Over Author "Richardeau, Frédéric" Topic hardware_integratedcircuits
6 results on '"Richardeau, Frédéric"'

1. Sub-nanosecond delay CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

Author

Plinio, Bau, Cousineau, Marc, Cogo, Bernardo, RICHARDEAU, Frédéric, Sébastien, Vinnac, Flumian, Didier, Rouger, Nicolas, Convertisseurs Statiques (CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, IRT Saint Exupéry - Institut de Recherche Technologique, and Convertisseurs Statiques (LAPLACE-CS)

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, ComputingMilieux_MISCELLANEOUS
Abstract

International audience; This paper presents an AGD (active gate driver) implemented with a low voltage CMOS technology to control the dv/dt sequence of low voltage (100V) and high voltage (650V) GaN power transistors. Such an AGD can control and reduce the dv/dt of fast switching GaN devices with a reduced impact on switching losses. In the case of both low voltage and high voltage GaN fast switching transistors, such an AGD must have a total response time lower than 1ns. Therefore, introducing a feedback loop to control the dv/dt requires a specific design with a very high bandwidth (550MHz). Moreover, probing the vDS voltage and its derivative is quite challenging, as the voltage level is higher than the low voltage gate driver supply. The purpose of this work is to optimize a low voltage CMOS AGD with fully integrated functions, and implement such a solution in GaN-based power converters. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power ic.

Published
2019
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2. Global electro-thermal modelling and circuit-type simulation of SiC Mosfet power devices in short-circuit operation for critical system analysis

Author

Boige, François, RICHARDEAU, Frédéric, Lefebvre, Stéphane, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT), Convertisseurs Statiques (LAPLACE-CS), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Laboratoire d’Océanologie et de Géosciences (LOG) - UMR 8187 (LOG), Institut national des sciences de l'Univers (INSU - CNRS)-Université du Littoral Côte d'Opale (ULCO)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD [France-Nord]), Laboratoire de Ressources Halieutiques, Institut Français de Recherche pour l'Exploitation de la Mer (IFREMER), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Centre d'enseignement Cnam Paris (CNAM Paris), Conservatoire National des Arts et Métiers [CNAM] (CNAM), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Pagès, Nathalie, Richardeau, Frédéric, Convertisseurs Statiques (CS), École normale supérieure - Rennes (ENS Rennes)-Université Paris-Sud - Paris 11 (UP11)-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Gustave Eiffel (UNIV GUSTAVE EIFFEL)

Subjects
model validation, MOSFET, silicon carbide, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, short-circuit, electrothermal simulation, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; The purpose of this paper is to present, for the first time, a global transient electrothermal model and simulation results of commercially recent silicon carbide (SiC) power MOSFET devices. The developed models aim is faithfully transposing specifically experimental short-circuit (SC) behaviour of the studied components, ready-to-use for the analysis of an inverter-leg malfunctioning. After extensive experimentation, a thermal model of the SiC die allows to develop models of gate-leakage current and drain-source current during SC. After verifying the robustness of the proposed models, an original circuit-type with an easy implementation is performed using a commercial circuit simulation tool.

Published
2017

3. Realisation and characterisation of compact generic IGBT-based multiphase power converters using the two-chip multi-pole integration approach

Author

Lale, Adem, Videau, Nicolas, El Khadiry, Abdelilah, Bourennane, Abdelhakim, Richardeau, Frédéric, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J), Convertisseurs Statiques (CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, ANR, LAAS-CNRS / LAPLACE-CNRS, ANR-13-JS09-0008,ConvPlUS,Intégration ultime d'un système multicellulaire de commutation de puissance sur puce multi-pôles silicium.(2013), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Convertisseurs Statiques (LAPLACE-CS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
reverse conducting-IGBT (RC-IGBT), device simulation, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_INTEGRATEDCIRCUITS, monolithic switching cells, stray inductance measurement, Hardware_PERFORMANCEANDRELIABILITY, Power integration
Abstract

International audience; This paper deals with the integration of power converters. The proposed integration approach combines both monolithic integration in silicon and hybrid integration on a DBC/PCB substrate. This new approach allows to devise new power converter assemblies that are of higher performance and reliability as compared to the conventional one. In this paper we present the « two-chip » multi-pole integration approach that integrates a multi-phase converter within two generic monolithic macro-chips. To validate the approach, a common anode macro-chip and two RC-IGBTs were judiciously assembled on PCB substrate to realize a first setup designed as a H-bridge generic converter. First characterization results of the converter are provided in static and switching modes.

Published
2015

4. Switching Optimization of WBG Power Devices on Inverter Leg

Author

Rossignol, Timothé, RICHARDEAU, Frédéric, Blaquière, Jean-Marc, Risaletto, Damien, Senghor, F., Cousineau, Marc, AULAGNIER, GUILLAUME, Cousineau, Marc, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Technocentre Renault [Guyancourt], RENAULT, University of Toulouse, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique de Toulouse (INPT-ENSEEIHT), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées, Freescale Semiconductor (Freescale), and Freescale semiconductor

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, Switching optimization, Hardware_INTEGRATEDCIRCUITS, Wide band gap devices, Inverter leg, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; In this paper the authors are interested by the switching optimisation of a SiC Power MOSFET in an inverter leg. The authors explain their efforts to build a test-bench that allows the extremely fast switching measurement of this WBG (Wide Band-Gap) component. Then trade-off curves between the dv/dt versus the switching energy are presented. The parameters are the external gate resistor and an additional gate-drain capacitor. Finally, basic dv/dt models are proposed and compared with the experimental results.

Published
2013

5. Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

Author

Yazan Barazi, Nicolas Rouger, Jean-Marc Blaquiere, Frédéric Richardeau, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Richardeau, Frédéric, Centre National de la Recherche Scientifique (CNRS), and Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
Fault under load, Computer science, 020209 energy, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Gate-charge, Robustness (computer science), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, SiC MOSFET, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Robustness, Hard switching fault, Power device, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Charge (physics), Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), [SPI.NRJ] Engineering Sciences [physics]/Electric power, Hardware_LOGICDESIGN
Abstract

International audience; This paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond-150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board).

Published
2021
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6. Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Author

Wadia Jouha, Stephane Azzopardi, Frédéric Richardeau, Richardeau, Frédéric, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, and Safran Tech

Subjects
Materials science, Thermal runaway, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, Planar, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Voltage source, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Power density, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), Optoelectronics, business, Failure mode and effects analysis, Short circuit, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe "Fail-To-Open" (FTO) mode in planar power SiC MOSFET devices under shortcircuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm²) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e VBRmin / 2. The boundary of the power density between FTO and "Fail-To-Short" (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

Published
2021
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