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This paper reports on integrated FET-based terahertz detectors operating in discrete frequencies spanning from 0.7-3.6THz. They are fabricated in standard 180nm CMOS process technology, and occupies a 2.7×3.0 mm2 chip area. Based on the Dyakonov and Shur theory, multi-pixel detectors are implemented by strict performance optimization and process compatibility. The simulated results demonstrate a promising application in low-cost terahertz spectrometer and imaging fields.

This paper introduces the design, analysis and simulation results of a driver for high-speed silicon photonic modulators. To achieve the high swing and high linearity simultaneously, several broadband circuit topology and techniques are employed, including the pre-emphasis circuit, variable gain amplifier and push-pull output stage. The driver is implemented in a 130nm BiCMOS process, achieving 22GHz bandwidth, 4V PP output swing, 900mW power consumption in the post-layout simulation.

The performance requirements of phase-locked loops (PLL) for the emerging applications such 5G and IoT are continuously growing. Compared with the conventional single-path loop based PLL, including the charge pump based PLL, sub-sampling PLL and all-digital PLL, the hybrid dual-path loop based PLL architecture (HDL-PLL) can combine the advantages of all these three kinds of single-path loop based PLL to achieve better performances. This paper first gives an overview of the basics, advantages, and the recent research progress of HDL-PLL. Then, two design examples based on our recent research with their measurement results are introduced to show that the HDL-PLL architecture can effectively improve the PLL performances.

A 50Gb/s PAM-4 optical receiver with Silicon Photonic (Si-Ph) photodiode (PD) and CMOS linear transimpedance amplifier (TIA) is presented. To optimize both noise and bandwidth, a two-stage front-end architecture—a high gain-low bandwidth TIA followed by a two-stage continuous time linear equalizer (CTLE) is adopted. Gain adjustment of the entire link is achieved by adjusting the TIA feedback resistor and the voltage of variable gain amplifier (VGA) to ensure that the receiver analog front-end (AFE) remains linear over the entire photocurrent input range. The chip has been realized in 40nm CMOS process. Experimental results show the TIA achieves 66dBΩ transimpedance gain, 24.4GHz bandwidth, 20dB gain dynamic range, maximum overload current 2mA, and differential output swing of 400mV. The total power consumption of the chip is 125.4mW.

This paper presents a terahertz source using standard CMOS process. The terahertz source is implemented with 4 mutual coupling oscillator cores based on injection locking theory. The push-push architecture is adopted in each oscillator core to generate the fourth harmonic signal. Moreover, on-chip patch antenna is integrated with each oscillator to radiate the output power. Frequency tuning is achieved by changing the phase shift between adjacent oscillators. The simulation results show that the source operates at the fundamental frequency of 86.5 GHz. The simulated fourth harmonic output power of each core is -15 dBm and the phase noise is -115 dBc/Hz at 10 MHz offset.

This paper presents a high-speed 2b/cycle SAR ADC. By resolving their comparison time with a 1-bit TDC, the number of comparators are reduced to two instead of three in a conventional 2b/cycle SAR ADC, which benefits power and linearity simultaneously. The proposed capacitor-halving switching method can realize the same input common-mode (CM) voltage variations on two comparators during the conversion phase. A simple novel high-speed dynamic SAR logic is developed to achieve the direct and fast control from the comparator to DAC arrays. Moreover, a simplified double-tail comparator is presented to accelerate the voltage comparisons. A 8-b prototype ADC is designed in 28-nm CMOS process, operating at a 1-V supply voltage. The simulated (including noise) results show that under a 1-GS/s sampling rate, the ADC achieves a SFDR of 63.4 dB and a SNDR of 46.5 dB at Nyquist frequency and consumes 2.2-mW power, leading to a Walden FoM of 12.8 fJ/conv.-step.

This paper proposes a CMOS fully integrated 860-GHz terahertz (THz) sensor. The sensor integrates a single-NMOS THz detector, a low-noise chopper instrumentation amplifier and a high-resolution ΔΣ-ADC. The detector consists of a novel on-chip grounded patch antenna and a source-feeding NMOS field-effect transistor (FET) of the minimum size. A microstrip transmission line is designed to improve the power transfer efficiency between the antenna and the NMOS transistor. A notch filter is proposed to improve detector performance. To enable the theoretical analysis of the operation of the THz detector and the formulation of design guidelines, we propose a THz-FET device model in which a source-coupled FET for THz detection is modeled as a dc voltage source with a resistor. The model indicates that an FET with the minimum physical dimensions for a given CMOS process can produce the maximum output signal. The sensor is implemented in a 180-nm standard CMOS process. The detector achieves a voltage responsivity of 3.3 kV/W and an NEP of 106 pW/Hz1/2 at 860 GHz. The sensor noise and the readout circuit noise are 10.81 and 2.03 μ Vrms, respectively. The sensor obtains clear raster-scanning transmission images under continuous THz illumination.

This paper presents a dual 28Gb/s modulator driver with on-chip PAM4 clock and data recovery (CDR) in 40nm CMOS. Used in the 400G Ethernet, 56Gb/s PAM4 signal is recovered by the CDR and demodulates into dual-28Gb/s NRZ data streams to drive the silicon photonic MZM DAC. Push-pull driver cells are employed to reuse the current for power saving with high-swing output. A digital-assisted distributed topology is proposed, extending the driver bandwidth and enabling low-power flexible pre-emphasis within each segment. Precise retiming is implemented by phase interpolation for the velocity match both in distributed driver segments and MZM DAC segments. Measurement results show the CDR+driver achieves 4Vpp differential voltage swing, 1.78ps RMS jitter and 1.34W power consumption (including PAM4 CDR and dual-channel driver) at 50Gb/s PAM4 input, while the standalone driver contributes to 1.5ps RMS jitter at 28Gb/s NRZ outputs.

This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc.

In this paper, the physical process of laser transmitting is modelled and analyzed, and this model is very helpful to analyze the requirements of different pixel structures on the frequency of laser emitter. In order to design the active quench circuit better, an accurate SPAD model is built with the Verilog-A description language. Then the circuit is presented and designed in 0.13um SiGe BiCMOS technology.

A 32×24 digital CMOS terahertz image sensor for 25 fps imaging at 860 GHz is presented. Pixel with DRC free structure is proposed and column parallel readout architecture is employed. The sensor array and the readout circuits are fully integrated into one single silicon chip in 180 nm CMOS process. Measured averaged room-temperature responsivity of single pixel is 1.28 kV/W at 860 GHz. The THz image sensor can operate up to 25 fps under continuous–wave illumination, and we acquired a video of a rotating blade chopping the backward wave oscillator (BWO) source beam, and the rotating blade can be clearly distinguished in the video.

This paper proposes passive and semi-passive wireless temperature and humidity sensors based on electronic product code (EPC) global Class-1 Generation-2 UHF communication protocol. The wireless sensors consist of a sensor key chip and off-chip temperature and humidity sensors. The sensor key chip integrates RF/analog front-end circuit, digital baseband processor, nonvolatile memory, on-chip temperature sensor, and sensor interface. The sensor interface connects the off-chip sensors and the sensor key chip. The sensor key chip with the on-chip temperature sensor can operate without battery power (passive mode), and also can co-operate with the off-chip temperature and humidity sensors powered by battery (semi-passive mode). The RF/analog front-end circuit provides the dc power to the sensor key chip and communicates with the interrogator passively. Advanced low-power techniques are adopted to reduce the power consumption of the sensor key chip. The sensor key chip is fabricated in 0.18- $\mu $ m CMOS process. In passive mode, the maximum wireless sensitivity of on-chip sensor is −15.1/−11.2 dBm for reading and sensing operation, respectively, and the temperature sensing error is −1 °C/0.8 °C over operating range from −20 °C to 50 °C. It achieves a reading/sensing distance of over 9.5/6 m with 4-W effective isotropic radiated power (EIRP) by the commercial interrogator. In semi-passive mode, the temperature and humidity sensing distance of off-chip sensors is 2.7 m.

A low power 8T global shutter pixel with extended FD voltage swing range is proposed for large format high speed CMOS image sensor. The pixel has a negative threshold reset transistor, two in-pixel source followers, and a sample-and-hold circuit. The in-pixel first source follower is employed for reducing the pixel average current and maximum transient current. The negative threshold reset transistor is applied to extend the voltage swing of FD. Using pixel level sample-and-hold circuit, the kTC noise on FD node can be effectively nullified by correlated double sampling operation. A high speed 1000 fps 256×256 CMOS image sensor is implemented in 0.18 μm CMOS process. Two 10-bit cyclic ADC arrays are integrated in this prototype sensor chip. The active area of the chip is 10 mm×7 mm with a pixel size of 14 μm×14 μm. The developed sensor achieves an average current of 23 nA per pixel, a maximum transit current per pixel as low as 1113 nA, and a large FD voltage swing of 1.78 V. The sensor temporal noise level is 103 e- and full well capacity has 27000 e- which results in 48.3 dB signal dynamic range.

A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.

This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed. The prototype was fabricated using 65 nm standard CMOS technology. At a 1.2-V supply and 100MS/s, the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB. The ADC core consumes only 3.1 mW, resulting in a figure of merit (FOM) of 30.27 fJ/conversion-step and occupies an active area of only 90um × 98um(0.009mm2).

This paper proposes a fully-integrated 860-GHz terahertz wave sensor. The sensor integrates a terahertz detector and readout circuit in 180-nm standard CMOS process. The readout circuit consists of a low-noise instrumentation amplifier and a high-resolution AZ-ADC. Transmissive imaging without source modulation (no lock-in technique required) is realized using the sensor. The detector consists of a novel on-chip grounded patch antenna, a source-feeding NMOS field effect transistor and matching networks. A quarter-wavelength microstrip transmission line is designed to connect the gate of the NMOS transistor to eliminate the influence of bonding wire and pad. The measured maximum voltage responsivity (Rv) and minimum noise equivalent power (NEP) of the detector at 860 GHz are 3.3 kV/W and 106 pW/Hz1/2, respectively. The measured readout circuit noise is 2. 03 μVrms.

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on mosfet based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the mosfet based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

This paper proposes an ultra-low power CMOS random number generator (RNG), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 μm CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 μW. This novel circuit is a promising unit for low power system and communication applications.

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

A source-switched charge pump (SSCP) with reverse leakage compensation technique is proposed to reduce spur level of wideband PLL induced by the reverse sub-threshold leakage of the charge pump. This technique can set the source–drain voltage of current-source N-type MOS (NMOS)/P-type MOS to be close to zero at off-state of the charge pump and thus reduce the reverse leakage. Compared with the conventional SSCP, only one NMOS capacitor, two CMOS switches and two inverters are added in the proposed charge pump. So, there is negligible extra power and extra area cost. A 0.7–1.6 GHz PLL is designed with the conventional and the proposed charge pumps in 65 nm CMOS process. Simulation results show the proposed SSCP can reduce orders of the magnitude of the reverse leakage without the penalty of current matching, compared with the conventional charge pump. The PLL with the proposed charge pump achieves up to 28 dB spur level reduction.

This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed. The prototype was fabricated using 65 nm standard CMOS technology. At a 1.2-V supply and 100 MS/s, the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB. The ADC core consumes only 3.1 mW, resulting in a figure of merit (FOM) of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm2.

This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm 2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

In this paper, we propose a compact ring-oscillator-based self-biased phase-locked loop (SBPLL) for system-on-chip (SoC) clock generation. It adopts the proposed triple-well NMOS source degeneration voltage-to-current (V–I) converter instead of the operational amplifier (OPAMP) based V–I converter and a proposed simple start-up circuit with a negligible area to save power and area. The SBPLL is implemented in the 0.18 µm CMOS process, and it occupies 0.048 mm2 active core. The measurement results show the SBPLL can generate output frequency in a wide range from 300 MHz to 1.125 GHz with a constant loop bandwidth that is around 5 MHz and a relatively low jitter performance that is less than 4.9 mUI over the entire covered frequency range. From −20 to 70 °C the rms jitter variation and loop bandwidth variation at 1.125 GHz are 0.2 ps and 350 kHz, respectively. The rms jitter performance variation of all covered frequency points is less than 10% in the supply range from 1.5 to 1.7 V. Such SBPLL shows robustness over environmental variation. The maximum power consumption is 5.6 mW with 1.6 V supply at an output frequency of 1.125 GHz.

This paper presents a novel low power baseband transceiver for wireless body area network (WBAN). This design includes a low complexity physical layer which is compatible with IEEE 802.15.4 and one optimal baseband operating scheme to reduce system power consumption. And the proposed channel codec has been integrated to improve anti-noise performance and energy efficiency. The chip is fabricated in 0.18 μm CMOS technology. The lowest power dissipation is 6.1 μW for TX and 7.2 μW for RX at 1.0V. Measurement results show energy efficiency is 19.6 pJ/bit for TX and 24.5 pJ/bit for RX at 5 Mbps.

A low power compact CMOS programmable temperature switch with process compensation is presented. Its threshold temperature T th can be programmed by a digital signal. The operating principle of the temperature switch is theoretically explained. We adopt a simple circuit architecture and a subthreshold CMOS circuit technique to reduce the chip size and the power consumption. A process compensation circuit is designed to compensate the threshold temperature T th variation automatically. The switch circuit is implemented in a standard 0.18um CMOS process. The measured results show that the temperature switch can be programmed to perform the switch operation at 12 different threshold temperature T th s from 45°C–100°C with a 5°C increment. The chip core area is 0.03mm2 and the power consumption is less than 1uA at 1.8V power supply.

A methodology is presented for predicting the phase noise of the ΣΔ Fractional-N Frequency Synthesize that is both accurate and efficient based on sampling the noise voltage in the time domain. An accurate Voltage Control Oscillator (VCO) noise model is presented, including both thermal noise and 1/f noise. The behavioral model provides a great speed-up over the transistor level simulation and an accurate phase noise prediction.

A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail‥1

In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated. An eight-stage charge pump circuit with each pumping capacitance of 0.5pF has been implemented in a 0.18µm standard CMOS process. The measured results show that the output voltage reaches 8.4V with 44MΩ resistive load under the supply voltage of 1.5V and clock frequency of 0.78MHz. The clock driver and the charge pump totally consume a current of 3µA.

This paper proposes a low power flexible programmable gain amplifier (PGA) with DC Offset cancellation for software defined radio front-ends. PGA consists of three-stage amplifiers which includes variable gain amplifier (VGA) and DC offset cancellation circuits. It uses high-pass filtering (HPF) and continuous-time feedback (CTF) techniques to cancel DC offset in the circuit. In VGA, a new technique is proposed to reduce the power consumption. PGA circuit is designed in 0.13um CMOS technology. Its power consumption is 0.2mA to 3.1mA at a 1.2V supply voltage.

This paper presents a novel RFID tag chip with temperature sensor in 0.18μm standard CMOS process. It consists of four blocks: RF/analog front-end circuit, 192-bit non-volatile memory (NVM), temperature sensor and digital baseband circuit. A CMOS UHF rectifier with dynamic bias using switch capacitor is proposed to improve the efficiency of rectification, while avoiding using costly Schottky diodes. We design a 192-bit NVM in standard CMOS process based on FN tunneling phenomenon with extremely small current density. It dissipates only 1.8μW/3.6μW for reading/writing operation. A 0.8μW smart temperature sensor with ±1°C resolution without power hungry ADCs is achieved. As a result, the power consumption is 5.8μW, 6.8μW, and 8.6μW for reading sensor, reading NVM and writing NVM respectively. The chip core area is 0.6mm2 in 0.18μm CMOS process.

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18µM standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8µA (3.6µA) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

This paper proposes novel multiple-valued (MV) logic gates by using asymmetric single-electron transistors (SETs). Asymmetric single-electron transistors have two tunneling junctions with largely different resistances and capacitances. We fully exploited the unique Coulomb staircase characteristic of asymmetric SETs to compactly finish logic operations. We build MV literal gates with wide range of radixes by using a pair of asymmetric SETs. We showed that, arbitrary radix-4 literal gate can be realized using a pair of asymmetric SETs. We also proposed MV analog-digital conversion circuits. The MV logic gates have very compact structures and low power dissipation.

Simple and compact multi-path switching devices for multi-valued decision diagram (MDD)-based logic circuits are designed, fabricated and characterized. The devices switch multiple exit branches for electrons entering from an entry branch, according to multi-valued input. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages. The gate threshold voltage is controlled by precise design of gate structures and sizes in nanometer scale. The operation principle of the device is described using a simple analytical model. Ternary-path switching devices are demonstrated using AlGaAs/GaAs etched nanowire junctions together with nanometer-scale Schottky wrap gates (WPGs) and in-plane gates (IPGs).

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mum 1P4M standard CMOS logic process and the core area is 0.06 mm2. The measured results indicate that the typical write/erase time is 10 ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 muA for program and 1.2 muA for read at a 1.6 V power supply.

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18 ?m 1P3M standard CMOS process. The chip area is 0.28 mm2 excluding test pads. Its power consumption is 25 ?W under 1.1 V power supply.

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45ï¼Â120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator and the single-electron multiple-valued memories (SEMVs). The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

This paper presents a fully integrated CMOS IEEE 802.11b/g WLAN radio transceiver chip with a novel local oscillator (LO) leakage auto calibration scheme. The transceiver chip is based on direct-conversion transmitter and receiver architecture and integrated in 0.25mum CMOS process. The noise figure is less than 5dB in a receive path. The inherent LO-leakage of direct-conversion transmitter is cancelled perfectly by using the proposed auto calibration method. The consumption currents of the receiver and transmitter are 120mA and 110mA at 2.5V power supply, respectively. Many kinds of cards and APs, which is made of this radio chip and homemade BB+MAC chip, have come into market.

This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter (LPF) is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A modified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compensation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consumption is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.

The paper proposes a high-speed target tracking CMOS image sensor. The target tracking CMOS image sensor consists of an image sensor array, row-parallel processors, a controller and a SRAM. It implements two novel concise algorithms that composed of efficient operations: such as collision detection, separation detection and position extraction. A 64 times 64 pixel array high-speed target tracking CMOS image sensor chip was implemented in using 0.35 mum 2P4M CMOS process. An N-well/P-sub SAB diode without salicide is used as photodiode in the image sensor. The chip size is 4.5 mm times 2.5 mm. The measured results demonstrated that the chip can perform target tracking at the rate of 1000 fps with more functionality and less area than the reported digital chips. The chip power consumption is 30 mW at the main clock of 20 MHz.

The paper presents a fully integrated two-receive-path and one-transmit-path CMOS radio transceiver chip compliant with 2.4GHz IEEE802.11b/g WLAN standards. The transceiver chip is based on direct-conversion architecture and integrates LNAs, mixers, filters, VGA, frequency synthesizer with on-chip VCO and voltage reference circuit in 0.25/spl mu/m CMOS process. It can improve the SNR characteristic of the communication system about 3/spl sim/6 dB. It increases the cover-range and reduces the influence of the multipath effect significantly. The noise figure is less than 5dB in a receive-path. The consumption currents of the receivers and transmitter are 120mA and 110mA at 2.5V power supply, respectively.

We designed a low power low phase noise phase locked loop (PLL) frequency synthesizer for 2.4 GHz wireless communication applications. Current reusing technique and triple-well NMOS transistors are applied to reduce power consumption and improve phase noise performance of the voltage controlled oscillator (VCO), respectively. The synthesizer has a fast locking mode that uses frequency presetting technique to greatly shorten the locking time. The synthesizer was implemented in 0.18 µm CMOS process. The chip core area is 1.49 mm2. Measured results show that the output frequency tuning range is 2.16–2.55 GHz. The phase noise is −124.18 dBc/Hz at 1 MHz from a 2.4 GHz carrier. The power consumption is 4.98 mW and the locking time in fast locking mode is about 4 µs.

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

A high-speed CMOS image sensor for real-time vision chip is proposed. The high-speed CMOS image sensor consists of CMOS photodiode array, correlated double sampling(CDS) array, programmable gain amplifier(PGA) array, area-efficient single-slope analog-to-digital converter(ADC) array and controller circuit. It can perform the image capturing and row-parallel signal processing. It outputs digital signal or digital image at a frame rate of over1000 frame/s. It can reduce the fixed pattern noise(FPN) and amplify(or shrink) the output signals of the photodiode array to maintain the amplitude of the signal in row-parallel fashion. It can continuously perform8-bit ADC conversion in row-parallel. A128 pixel×128 pixel image sensor with128 rows of CDS, PGA and single-slope ADC is fabricated by using0.18μm1P6M CMOS process. The chip size is2.2 mm×2.6 mm. The measured results demonstrate that the designed chip can perform high-speed real-time optical signal capturing and processing. It can be applied to the real-time vision chip system.