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An ultra-low power CMOS random number generator
- Source :
- Solid-State Electronics. 52:233-238
- Publication Year :
- 2008
- Publisher :
- Elsevier BV, 2008.
-
Abstract
- This paper proposes an ultra-low power CMOS random number generator (RNG), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 μm CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 μW. This novel circuit is a promising unit for low power system and communication applications.
- Subjects :
- Engineering
business.industry
Local oscillator
Electrical engineering
Delay line oscillator
Hardware_PERFORMANCEANDRELIABILITY
Variable-frequency oscillator
Condensed Matter::Mesoscopic Systems and Quantum Hall Effect
Condensed Matter Physics
Electronic, Optical and Magnetic Materials
Blocking oscillator
Vackář oscillator
Voltage-controlled oscillator
Hardware_INTEGRATEDCIRCUITS
Materials Chemistry
Electronic engineering
Pierce oscillator
Digitally controlled oscillator
Electrical and Electronic Engineering
business
Subjects
Details
- ISSN :
- 00381101
- Volume :
- 52
- Database :
- OpenAIRE
- Journal :
- Solid-State Electronics
- Accession number :
- edsair.doi...........ef000114d221bd9ca00d81b36cbca74c