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A generalized structure that is capable of implementing power-law filters derived from 1st and 2nd-order mother filter functions is presented in this work. This is achieved thanks to the employment of Operational Transconductance Amplifiers (OTAs) as active elements, because of the electronic tuning capability of their transconductance parameter. Appropriate design examples are provided and the performance of the introduced structure is evaluated through simulation results using the Cadence Integrated Circuits (IC) design suite and Metal Oxide Semiconductor (MOS) transistors models available from the Austria Mikro Systeme (AMS) 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process.

This paper introduces a fractional-order eardrum Type-II model, which is derived using fractional calculus to reduce the number of elements compared to its integer-order counterpart. The proposed fractional-order model parameters are extracted and compared using five meta-heuristic optimization techniques. The CMOS implementation of the model is performed using the Design Kit of the Austria Mikro Systeme (AMS) 0.35 $$\upmu {\hbox {m}}$$ CMOS process, while the simulations have been performed using the Cadence IC design suite.

A novel resistorless topology for implementing fractional-order capacitor emulators, based on the employment of Operational Transconductance Amplifiers (OTAs) as active elements, is presented in this paper. The benefits of this topology are its simplicity in terms of component count, compared to other existing topologies in the literature, in addition to its electronic tunability. The performance of the presented topology is evaluated using Cadence and the 0.35 μm CMOS process Design Kit from Austria Mikro Systeme. Experimental results using commercial OTA chips are also provided, where the emulation of fractional-order capacitors is demonstrated.

Ultra-low-voltage sinh-domain implementation of delayed inertial neuron is introduced in this paper. The complex dynamical behavior of the neuron has been verified using three different activation functions, namely tanh, unipolar sigmoidal and bipolar sigmoidal. The networks containing two and four neurons have been designed, and their complex dynamical behavior has also been verified. The proposed implementation vis-a-vis the already reported designs offers the benefits of: (1) low-voltage operation, (2) integrability, due to resistor-less design and the employment of only grounded components, (3) electronic tunability of performance parameters by external currents, which adds flexibility to the proposed designs even after their final fabrication, (4) absence of inductors as, in contrast to reported designs, the delay has been implemented using component substitution method where inductors have been replaced by emulated inductors and (5) low-power implementation due to the inherent class AB nature of sinh-domain technique. Besides, for the first time, the complex dynamical behavior of four-neuron delayed inertial network has been implemented and its functioning for different activations functions has been considered and verified. HSPICE simulator tool and TSMC 130 nm CMOS process were used to evaluate and verify the correct functioning of the model.

A novel implementation of a fractional-order parallel resonator, capable of operating in a ±0.5 V power supply voltage environment, is presented in this work. Compared to the corresponding already published structures, it offers the benefit of reduced circuit complexity, due to the utilization of very simple voltage-mode 1st-order filter sections, leading also to reduction in the dc power consumption. Electronic tuning capability is another attractive feature of the proposed structure achieved using programmable MOS transistor transconductance parameters.

This brief presents a universal filter based on multiple-input fully differential difference amplifier (FDDA) that is suitable for extremely low-power low-voltage applications. The filter employs three FDDAs, eight resistors, four capacitors and can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses. Thanks to the utilization of the multiple-input MOS transistor technique, one differential pair with an arbitrary number of inputs is required for constructing the FDDA. Therefore, unlike the previously published FDDA-based universal filters, the proposed filter has the simplest CMOS structure with less power consumption than those already published in the literature. The filter operates with 0.5 V, consumes 740 nW and exhibits rail-to-rail input common mode range. The dynamic range of the BP filter is 73 dB for 1% third intermodulation distortion. The circuit was designed in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process design kit, and the simulation results confirm the advantages of the proposed filter.

A low-pass fractional-order filter topology based on a single metal oxide semiconductor transistor is presented in this Letter. The filter is realized using a fractional-order capacitor fabricated using multi-walled carbon nanotubes. The electronic tuning capability of the filter’s frequency characteristics is achieved through a biasing current source. Experimental results are presented and compared with the theory.

A novel topology for simultaneous emulation of fractional-order capacitors and inductors is presented in this paper. In particular, only one control terminal is used in order to select the type of the element as well as its fractional order. This is achieved through an appropriate fitting of the expressions of the intermediate bias currents, in such a way that, eventually, only the adjustment of one main bias current is required. The performance of the proposed topology is evaluated through post-layout simulations using Cadence and Austria Mikro Systeme (AMS) 0.35 μ m CMOS process.

An electronically adjustable realization of the three-element Windkessel model, thanks to the employment of an Operational Transconductance Amplifier-based structure, is presented in this work. Instead of following the typical method where the fractional-order capacitor is substituted by its active emulator, in this case the whole impedance is considered for the implementation of the model. The approximation of the total impedance function is performed through the utilization of an appropriate curve-fitting-based technique, which, compared to the conventional method where the approximation of the Laplacian operator is performed, offers improved accuracy. The presented post-layout simulation results, obtained using the Cadence IC design suite and MOS transistors models provided by the Austria Mikro Systeme (AMS) CMOS process, confirm the correct operation of the developed topology.

This paper presents a new multiple-input single −output voltage-mode universal biquad filter based on multiple−input operational transconductance amplifiers (MI-OTA). This work demonstrates that the multiple-input OTA−based universal filter can provide more filtering responses and other benefits, compared to conventional OTA−based one. The filter provides electronic and orthogonal control of the natural frequency and the quality factor. Furthermore, a two-phase quadrature oscillator can be obtained by slightly modifying the proposed universal filter while the condition and frequency of oscillation can be controlled orthogonally and electronically. The performance of the proposed circuit is evaluated in Cadence environment using the TSMC $0.18~\mu \text{m}$ CMOS technology. The voltage supply is 1.2 V and the power dissipation of the MI−OTA is $24~\mu \text{W}$ . For 1% third intermodulation distortion (IMD3) the dynamic range of the band−pass filter is 78.6 dB. In addition, the proposed filter and oscillator are investigated through experiment tests using LM13700 commercially available OTA.

A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 mu m CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under +/- 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms.

An implementation of fractional-order controller suitable for a magnetic levitation system is presented in this work. It is constructed from operational amplifiers as active cells and the main offered benefit with regards to the conventional implementation is the reduced number of active component count. This is achieved thanks to the voltage summation operation offered by the operational amplifier. The performance of the controller has been evaluated by employing the OrCAD PSpice simulator and using the model of the OP07 operational amplifier discrete IC component.

The implementation of the Cole-Cole model, which describes the changes of the biceps tissue during fatigue exercises, is presented in this work. As the model parameters change with the subject under consideration, the electronic programming feature, offered by the proposed topology, is very important for achieving versatility of the scheme. This has been achieved through the utilization of the electronically dependent transconductance parameter of the Operational Transconductance Amplifiers, used for approximating the fractional-order capacitor and the passive resistors.

Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.

A novel universal biquad filter topology, realized using Operational Transconductance Amplifiers as active elements, is presented in this paper. It offers the benefits of orthogonal adjustment of the resonance frequency and the quality factor of the filter and, also, resistorless realization with grounded capacitors. The attractive characteristic is the requirement of single output Operational Transconductance Amplifies because in this way the implementation of the filter using commercially available discrete component ICs as OTAs is quite facilitated. Comparison with the literature shows that the proposed solution is the most beneficial from the active component count point of view. The behavior of the proposed topology is evaluated trough simulation results, using the OrCAD PSpice simulator, as well as through experimental results using the LM 13700 discrete component IC as Operational Transconductance Amplifier.

A fully integrated implementation of a parallel fractional-order resonator that employs together a fractional-order capacitor and a fractional-order inductor is proposed in this brief. The design utilizes current-controlled operational transconductance amplifiers as building blocks, designed, and fabricated in AMS ${0.35{-}\mu {\mathrm{ m}}}$ CMOS process and based on a second-order approximation of a fractional-order differentiator/integrator magnitude optimized in the range 10 Hz–700 Hz. An attractive benefit of the proposed scheme is its electronic tuning capability.

A fractional-order capacitor and inductor emulator, implemented using MOS transistors, instead of passive capacitors, is introduced in this paper. This is achieved using current mirrors as active elements, without passive resistors, and therefore reducing the circuit complexity and resulting in both a resistorless and capacitorless topology. The emulator has been designed by combining fractional-order differentiator or integrator topologies with a voltage-to-current converter. An important benefit from the design flexibility point of view is that the same topology could be used for emulating a fractional-order capacitor or inductor through an appropriate selection of the time constants and gain factors. Considering that the MOS transistors operate in the strong inversion region, it is feasible for this emulator to operate at high frequencies. The evaluation of the proposed topology has been performed using Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 $$\upmu \hbox {m}$$ CMOS process.

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/differentiation operation within the emulator stage. Also, a voltage-to-current converter, implemented using an Operational Transconductance Amplifier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and offers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modified version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.

Novel topologies of fractional-order filters, implemented using the internal gate-source capacitance of MOS transistors, are introduced in this paper. This has been achieved using current-mirrors as active elements, resulting into resistorless realizations due to the employment of the small-signal transconductance parameter of the MOS transistor. This also offers the capability for electronic tuning of the frequency characteristics of the derived filter structures. The evaluation of the proposed technique has been performed through the design of a generalized fractional-order filter, which is also digitally programmed in such way that the four standard filter functions are offered. The behavior of the filter has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.

The neurons are proven to show chaotic dynamical behavior, and due to this behavior, they find applications in several fields. Recently, the chaotic behavior of the neuron model using non-monotonous Liao’s activation function was described and its design using op-amp was presented. The presented design is a high-voltage one and is not integrable, as both passive resistors and inductors have been employed. Besides, most of the components are of floating type, which are difficult to design on an integrated chip. In addition, only integer-order design has been considered. In this paper, an ultra-low-voltage sinh-domain implementation of the neuron model has been introduced. Moreover, for the first time, the fractional-order implementation of the model has also been presented. The design offers the advantages of: (a) low-voltage implementation, (b) integrable design, (c) resistor and inductor less design, (d) using only grounded components, and (e) low-power design due to the inherent class AB nature of sinh-domain technique. The proper functioning of the model has been verified through different cases where the time constant of the integrator, delay and fractional order have been varied. The behavior of the neuron models is evaluated through HSPICE simulator using the metal oxide semiconductor transistor (MOSFET) models provided by Taiwan Semiconductor Manufacturing Company Limited (TSMC) 130 nm complementary metal oxide (CMOS) process.

Fractional-order capacitors are the core building blocks for implementing fractional-order circuits. Due to the absence of their commercial availability, they can be approximated through appropriately configured passive or active integer-order element topologies. Such a topology, constructed using Operational Transconductance Amplifiers (OTAs) and capacitors has been implemented in monolithic form through the AMS 0.35 μm CMOS process, and the fabricated chips are employed here for the experimental evaluation of the behavior of networks constructed from fractional-order capacitors connected in series or in parallel.

In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage operation capabilities is presented. Simplicity is other important feature so that the whole circuit is composed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-threshold region. The required current-controlled gain stage has been implemented using an appropriate translinear loop which is fed by the output of a current subtraction stage, realized through the employment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is evaluated through simulation results, using the Cadence suite and MOS transistors models provided by the Austria Mikro Systeme 0.35 μ m CMOS process. The differential gain was 20 – 40 dB , the Common-Mode Rejection Ratio (CMRR) was 44.4 – 48.9 dB , achieved at power dissipation 72.75 – 386.1 nW . The bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2 % for an input signal with amplitude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier has been employed for removing the noise component in electrocardiogram signals.

A multi-function fractional-order filter topology, realized through the utilization of the partial fraction expansion tool, is introduced in this paper. Thanks to the employment of the log-domain technique, the topology offers the benefit of the electronic tuning of the filter characteristics and, also, reduced MOS transistor count in comparison with the corresponding already published structures. The evaluation of the behavior of the filters has been performed using the Cadence software and MOS transistor models provided by the Austria Mikro Systeme $0.35\mu m$ CMOS process.

This paper introduces a novel design for implementing a fractional-order $I^{\lambda}D^{\mu}$ DC motor controller, where only one active element is required. This element is a second generation current conveyor, capable of working in a low-voltage environment. The main advantage, the proposed implementation offers compared to the corresponding schemes in the literature, is a simple structure of low circuit complexity and reduced number of transistor count. The performance of the controller is evaluated using the Cadence software and MOS transistor models provided by the Austria Mikro Systeme $\mathbf{0.35}\mu \mathbf{m}$ CMOS process.

In this work, a novel implementation of a tunable fractional-order bandpass filter of order 2α is proposed. The transfer function of the presented filter is approximated using the second-order Continued Fraction Expansion (CFE) approximation technique. The filter transfer function is realized using the Inverse Follow the Leader Feedback (IFLF) structure. The Operational Transconductance Amplifiers (OTAs) are used to implement the filter circuit. Furthermore, the proposed filter is tunable by varying the value of only one bias current, which adjust the value of α. The simulations are performed using Matlab and Cadence software with UMC 0.13µ m CMOS technology.

A novel topology that approximates the behavior of fractional-order lead/lag compensators is introduced in this work. This is achieved using the Pade’ approximation of the function of the lead/lag compensator by a rational integer-order function. Thanks to the employment of Operational Transconductance Amplifiers as active elements, the proposed scheme offers the benefit of electronic tuning capability of the characteristics of the compensator. In addition, the presented scheme is capable of implementing both types of compensators using the same topology. The performance of the proposed topology is evaluated using the Cadence software and MOS transistor models provided by the Austria Mikro Systeme 0.35μm CMOS process.

Novel fractional-order capacitor and inductor em-ulators are presented in this work, which offer fully electronic tunability of their characteristics and, simultaneously, reduced circuit complexity compared to those already introduced in the literature. This has been achieved through the utilization of the log-domain filtering for implementing the approximation of the required fractional-order differentiation/integration stages. The behavior of the presented topology is evaluated using the Cadence software and MOS transistor models provided by the 0.35μm Austria Mikro Systeme CMOS process.

A fractional-order implementation of the model of the arterial viscoelasticity is presented in this work. The main attractive offered benefit is that all the states of the arterial viscoelasticity are implemented by the same core, just by adjusting appropriate dc bias currents. This has been achieved through the proposal of an enhanced fractional-order inductor emulator, where the characteristics of the element can be independently adjusted. The behavior of the designed model has been evaluated through post-layout simulation results, using the Cadence IC design suite and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35μm CMOS process.

An implementation of the cardiac tissue electrode interface fractional-order model is presented in this work. The realization of the required fractional-order capacitor emulator has been performed in such a way that the spread of the capacitor and transconductance values is minimized. Thanks to the employment of Operational Transconductance Amplifiers (OTAs) as active cells, the proposed scheme offers the benefits of electronic tuning and capability of implementation in monolithic form.

A multi-function fractional-order filter topology, constructed from 2 MOS transistors only, is introduced in this paper. The required time-constants are realized through the utilization of the small-signal transconductance parameter of the MOS transistor, offering electronic adjustment of the frequency characteristics of the derived filters. The main attractive offered benefit, in comparison with the literature, is the significant reduction of MOS transistor count and, consequently, the reduced power dissipation. The behavior of the filters is evaluated using the Cadence software and MOS transistor models provided by the $0.35\mu m$ Austria Mikro Systeme CMOS process.

A simple realization of the fractional-order Mihalas-Niebur neuron model is presented in this work. The required low-pass filter is implemented using current-mirrors offering simple circuitry and, also, electronic tunability of the realized time-constant. Due to the limited bandwidth required for this application, the necessary fractional-order capacitor is realized using an appropriately configured second-order RC network. The proposed realization highlights the connection between the fractional-order and the frequency spiking of the model through appropriate simulation results, which are derived via the Analog Design Environment of Cadence software, using MOS transistor models provided by the AMS $0.35\mu\mathrm{m}$ process.

An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 m Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation.

Summary Novel topologies of fractional-order generalized filters are introduced in this paper. These offer the following benefits: (1) realization of lowpass, highpass, bandpass, allpass, or bandstop filter functions by the same topology; (2) resistorless realizations; (3) electronic adjustment of their frequency characteristics as well as their order; and (4) employment of only grounded capacitors. All the above have been achieved using Operational Transconductance Amplifiers as active elements and appropriate multi-feedback topologies. The behavior of the proposed designs is verified through simulation results using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35-µm complementary metal–oxide–semiconductor process. Copyright © 2016 John Wiley & Sons, Ltd.

A novel topology suitable for emulating fractional-order capacitors and inductors using current excitation is achieved using a fractional-order differentiator/integrator block and appropriately configured Operational Transconductance Amplifiers. The scheme is capable of emulating both fractional-order capacitors and fractional-order inductors without any modifications to its structure. This implementation allows for electronic tuning of the order, capacitance/inductance, and bandwidth of operation by modification of only the bias current. Post-layout simulation results of the impedance magnitude and phase confirm the correct emulated behavior of both fractional-order capacitors and inductors. Two examples highlight the applications of this topology in i) realizing a fractional-order bandpass filter and ii) emulating a Cole-impedance model for biological applications. For both examples the characteristics of each circuit are validated in simulation.

A low frequency relaxation oscillator is designed using a super-capacitor. An accurate analytical expression for the oscillation frequency is derived based on a fractional-order super-capacitor model composed of a resistance in series with a Constant Phase Element (CPE) whose pseudo-capacitance and dispersion coefficient are determined using impedance spectroscopy measurements. Experimental results confirm our theoretical analysis.

This paper proposes a new design of a 2 α -order fractional-order band-pass filter with a tunability feature. The proposed filter is approximated with the second-order approximations of the Continued Fraction Expansion and the Matsuda. The proposed circuit is used to realize the filter transfer function based on the Inverse Follow the Leader Feedback configuration with Operational Transconductance Amplifiers . Moreover, the proposed filter can be adjusted by changing a single parameter, which is the bias current I bias . A comparison with the recent previous works is performed showing the advantage of the electronic tuning feature using one bias current value in the proposed filter. Sensitivity analysis is conducted to investigate circuit parameter variation, such as capacitance and gain factors. Stability analysis is performed by studying the poles’ location and movement versus the filter parameters. Besides, the effect of transistor mismatch is evaluated using Monte Carlo analysis. Matlab and Cadence software with UMC technology of 0.13μm CMOS are used for the simulations to verify the proposed implementation.

A new class of quadrature phase oscillators based on cross-coupled differential pairs is introduced. This class contains eight possible circuits which produce four output voltages with phase differences of $\pm\pi$ or $\pm\pi/2$, depending on the choice of output node, and does not require balanced differential-pair loads. Phase error analysis is provided along with experimental and simulation results using discrete MOS and BJT transistors as a proof of concept.

Using fractional calculus, we analyze a classical switched-capacitor integrator when a fractional-order capacitor is employed in the feed-forward path. We show that using of a fractional-order capacitor, significantly large time constants can be realized with capacitances in the feedback path much smaller in value when compared with a conventional switched-capacitor integrator. Simulations and experimental results using a commercial super-capacitor with fractional-order characteristics confirmed via impedance spectroscopy are provided. Copyright © 2016 John Wiley & Sons, Ltd.

This paper deals with the design, analysis, computer simulation, and experimental measurement of fractional-order sinusoidal oscillator with two current conveyors, two resistors, and two fractional immittance elements. The used conveyor is based on the bulk-driven quasi-floating-gate technique in order to offer high threshold-to-supply voltage ratio and maximum input-to-supply voltage ratio. The supply voltage of the oscillator is 1 V, and the power consumption is $$74\,\upmu \hbox {W}$$74μW, and hence the proposed oscillator can be suitable for biomedical, portable, battery-powered, and other applications where the low-power consumption is critical. A number of equations along with graphs describing the theoretical properties of the oscillator are presented. The unique features of fractional-order oscillator are highlighted considering practical utilization, element computation, tuning, phase shift of output signals, sensitivities, etc. The simulations performed in the Cadence environment and the measurements of a real chip confirm the attractive features of the proposed oscillator.

The concept of emulating a constant phase element by an active scheme is presented in this work. Starting from a novel setup where the characteristics of the element could be easily derived, the emulation of the constant phase element is performed through a scheme that employs a differentiator and a voltage-to-current converter. The implementation of this scheme is done using operational transconductance amplifiers as active elements and uses grounded capacitors. The proposed emulator is accurate over five decades of frequency from (0.1 to 10 kHz) and offers independent electronic tunability of the constant phase element (i) magnitude (ii) phase angle and (iii) bandwidth of operation. Constant phase element designs currently available in the literature rely on using fixed passive RC ladder networks and thus lack flexibility and tunability. The behavior of the proposed design is verified through post-layout simulation results using Cadence and the 0.35 μm CMOS process Design Kit provided by the Austrian Micro Systems.

A digitally programmable low-voltage highly linear transconductor (G m stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5 V and consumes 36 μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35 μm CMOS AMIS process with total chip area 213 μm × 266 μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.

The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS.

A fractional-order model of the B&K type 4185 commercial ear simulator is introduced in this work. It is constructed from a series connection of an integer-order inductor and a fractional-order capacitor. The proposed model is much simpler than its corresponding integer-order counterpart and can easily be implemented using Operational Transconductance Amplifiers (OTAs) and grounded capacitors in a fully resistor-less structure. The proposed realization also offers electronic tuning capability of its characteristics through the adjustment of appropriate dc currents and is realizable in fully integrated form. Evaluation of the behavior of the proposed model is performed using Cadence and the Design Kit provided by the Austrian Micro Systems 0.35μm CMOS process.

Summary Fractional-order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0

Fractional-order filters as well as capacitor and inductor emulators, implemented using current-mirrors as active elements are presented in this work. Due to the utilization of the internal gate-source capacitance of MOS transistors or of the appropriately configured MOS transistors as capacitors, there is an absence of passive capacitors in the resulted structures. In addition, the small-signal transconductance parameter of the MOS transistors of current-mirrors is used for realizing the required resistors and, consequently, there is also an absence of passive resistors. The evaluation of the behavior of the proposed topologies has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35um CMOS process.

Fractional-order circuits for emulating the mechanical impedance model of the human respiratory system, as well as the wood tissue impedance model are presented in this work. This has been achieved using active emulators of fractional-order capacitors and inductors. Thanks to the employment of Operational Transconductance Amplifiers, the derived structures are resistorless and, also, their characteristics are electronically controlled through appropriate dc voltages/currents. Therefore, they offer design flexibility and modularity and could be used for emulating various types of tissues and biomedical systems. The performance of the provided designs has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35um CMOS process.

A new voltage-mode fractional-order oscillator, employing in total 12 Metal-Oxide-Semiconductor (MOS) transistors, is introduced in this paper. The proposed circuit is composed of two operational transconductance amplifiers, two inverting voltage buffers, one resistor, and two fractional-order capacitors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count and, therefore, simplicity of its structure. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The behavior of the proposed oscillator has been numerically studied using the MATLAB program, while its performance has been evaluated by SPICE simulations, using TSMC 0.18 μm Level-7 CMOS process parameters with ±I V supply voltages.

Wood tissue impedance is known to possess fractional-order characteristics which can be emulated using appropriately configured RC networks. However, this is not an optimum solution from the design flexibility point of view, due to the absence of on-line tunability of the characteristics of the emulated impedance. To overcome this difficulty, active emulators have been introduced, where the active elements are Operational Transconductance Amplifiers (OTAs). This offers electronically tunable structures capable of capturing the characteristics of the emulated tissue under different conditions. In addition, it is capable for implementation in monolithic form. In this work, an integrated emulator of the fractional-order wood tissue model for application in monitoring moisture gradients in wood products is presented. The operation of the proposed emulator is verified using the Cadence software and MOS transistor models provided by the AMS 0.35 μm CMOS process and confirmed to operate within the desired specifications.

In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation, and frequency of oscillation are shown. Various case examples are given while SPICE simulations using TSMC 0.35 µm level-3 CMOS process parameters with ±1.65 V supply voltages verify their operation and compare with theoretical ones.

This paper presents experimental results for a low-voltage (LV) low-power (LP) voltage rectifier realization, employing two differential difference amplifiers (DDA) as active elements.The proposed DDA is based on the recently presented technique named bulk-driven quasi-floating-gate that enables the circuit to work with 1 V power supply voltage, threshold-to-supply ($$V_{TH}$$VTH /$$V_{DD})$$VDD) ratio and modulation index factor $$(V_{pp.max} /V_{DD})$$(Vpp.max/VDD) equal to 70 and 90 %, respectively. The competitive features of the proposed structure compared with other state-of-the-art circuits are the capability for working under LV supply, with extended common mode voltage range and improved input transconductance. The proposed circuit was designed, simulated, and fabricated employing the Cadence platform and MOS transistors models provided by the 0.35 $$\upmu $$μm CMOS AMIS process. The total chip area was 213 $$\times $$× 266 $$\upmu \mathrm{{m}}^2$$μm2. The provided simulation and experimental results prove the attractive performances of the proposed rectifier topology.