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A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.

In this work, normally-off p-channel and n-channel heterojunction field-effect transistors (HFETs) were fabricated based on a p-GaN gate Al0.2Ga0.8N/Al0.05Ga0.95N HFET platform. For p-channel HFETs, normally-off operation and low gate leakage were obtained by using a recessed-gate structure and a 20 nm Al2O3 thin film grown by thermal atomic layer deposition as the gate insulator. The normally-off p-channel HFETs exhibited a threshold voltage of 105. By introducing an Al0.05Ga0.95N channel instead of a conventional GaN channel layer, the threshold voltage increased from 1.1 V to 1.5 V and the breakdown voltage almost doubled from 270 to 580 V for n-channel HFETs. These results indicate that n-channel and p-channel HFETs based on p-GaN/Al0.2Ga0.8N/Al0.05Ga0.95N heterostructures have a great potential for monolithic integration.

Low-frequency noise (LFN) performances are investigated in a normally-off GaN metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by utilizing the tetramethylammonium hydroxide (TMAH) wet etching. The normalized power spectral densities ($\text{S}_{Id}/\text{I}_{d}^{2})$ are measured and perfectly matched with both the correlated mobility fluctuations (CMF) and Hooge mobility fluctuations (HMF) noise models. From the curves of ($\text{S}_{Id}/\text{I}_{d}^{2})$ dependent on the gate overdrive voltage (Vg – $\text{V}_{th})^{-1}$ , it is also confirmed that the mobility fluctuations prevail in the fabricated GaN device. The calculated Hooge constants ($\alpha _{H}$) according to the (Vg – $\text{V}_{th}$) are obtained to be 10−2 ~ 10−3. The reason for the dominance of the mobility fluctuations and the relatively low $\alpha _{H}$ is attributed that the TMAH wet etching effectively removes the plasma etching damage and fully recovers the crystal quality of GaN channel. [ABSTRACT FROM AUTHOR]

Cascode topology which includes a high-voltage GaN and a low-voltage Si transistor is an attractive device concept, as it takes advantage of the low on-resistance of GaN while still being compatible with Si gate drivers. It demonstrates the highest threshold voltage among normally-off GaN devices, which is a favorable feature in power electronics. However, the observation of instability in power circuits using cascode devices highlights the need for a careful analysis to reveal the origins of this phenomenon, to fulfill the unique features of these devices in high efficiency and reliable power converters. In this letter, we demonstrate the presence of negative resistance in cascode devices, which explains the previously reported large-signal instabilities. We describe a theory to characterize this negative resistance behavior based on the subthreshold-voltage operation of the high-voltage GaN transistors, and propose guidelines to resolve this issue in cascode devices. Negative resistance behavior, although not favorable for a power transistor, is of great importance in high-frequency electronics, with applications in reflection-type power amplifiers. These results, together with the presented analysis, could guide the development of high-stability, low-loss devices for future efficient power converters. [ABSTRACT FROM AUTHOR]

• HF pretreatment prior to gate formation to improve gate leakage characteristics. • 3–4 orders of magnitude improvement in gate leakage was observed. • The mechanisms of the improved gate leakage was investigated. • The properties of the improved gate leakage with/without pretreatment were compared. We demonstrate the electrical performances of an AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) with low gate leakage current (I g). A low gate leakage current as low as the order of 10−11 A/mm was achieved from normally-off MIS-HEMT device (V th = 2.16 V) with a partially recessed gate, fluorine treatment, and ALD Al 2 O 3 gate dielectric layer. The gate leakage current decrease is attributed to the pre-treatment of the gate region with hydrofluoric acid (HF) and deionized water (DI) solution, which acts to remove the native oxide layer and thus decrease interface traps. X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) analyses demonstrate that the AlGaN surfaces are modified such that the surface roughness and native oxide introduced by the treatments used to achieve normally-off operation are remedied with the use of the pre-treatment. [ABSTRACT FROM AUTHOR]

In this letter, we present normally-off GaN-on-Si MOSFETs based on the combination of tri-gate with a short barrier recess to yield a large positive threshold voltage (${V}_{\text {TH}}$) while maintaining a low specific on resistance (R $_{ON, \text {SP}}$) and high current density (${I}_{\text {D}}$). The tri-gate structure offered excellent channel control, enhancing ${V}_{\text {TH}}$ from +0.3 V for the recessed to +1.4 V for the recessed tri-gate, along with a much reduced hysteresis in ${V}_{\text {TH}}$ , and a significantly increased transconductance (${g} _{\text {m}}$). Additional conduction channels at the sidewalls of the tri-gate trenches compensated the degradation in ON-resistance (${R} _{ON}$) from the gate recess, resulting in a small ${R} _{ON}$ of $7.32~\pm ~0.26~\Omega \cdot $ mm for ${L} _{\text {GD}}$ of $15~ {\mu }\text{m}$ and an increase in the maximum drain current (${I}_{\text {D}}^{\text {max}}$). In addition, the tri-gate inherently integrates a gate-connected field-plate (FP), which improved the breakdown voltage (${V} _{\text {BR}}$) and reduced the degradation in dynamic ${R} _{ON}$. With proper passivation techniques, these devices could be very promising as high-performance power switches for future power applications. [ABSTRACT FROM AUTHOR]

A tetramethyl ammonium hydroxide (TMAH)-treated normally-off Gallum nitride (GaN) metal-insulator-semiconductor field-effect transistor (MISFET) was fabricated and characterized using low-frequency noise (LFN) measurements in order to find the conduction mechanism and analyze the trapping behavior into the gate insulator as well as the GaN buffer layer. At the on-state, the noise spectra in the fabricated GaN device were 1/fγ properties with γ ≈ 1, which is explained by correlated mobility fluctuations (CMF). On the other hand, the device exhibited Lorentzian or generation-recombination (g-r) noises at the off-state due to deep-level trapping/de-trapping into the GaN buffer layer. The trap time constants (τi) calculated from the g-r noises became longer when the drain voltage increased up to 5 V, which was attributed to deep-level traps rather than shallow traps. The severe drain lag was also investigated from pulsed I-V measurement, which is supported by the noise behavior observed at the off-state.

A normally-OFF p-GaN gate AlGaN/GaN high-electron-mobility transistor with high ON-state resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) uniformity was realized using a self-terminated digital etching technique. ${R}_{ \mathrm{\scriptscriptstyle ON}}$ uniformity control was improved by simultaneously using an AlN etching stop layer in an epitaxial design and a novel digital etching procedure. Digital etching includes the multiple-cycle oxidation and the wet etching of p-GaN layers and provides easy control of p-GaN removal depth and surface damage reduction at the gate-to-drain and gate-to-source spacing areas. Low-frequency noise and pulse measurements indicated that device surface traps and current collapse phenomena were suppressed. [ABSTRACT FROM AUTHOR]

This paper describes characteristics of normally-off mode GaN MISFETs fabricated on free-standing GaN substrates with high drain current Idss and specific low leakage current between adjacent devices. Nitrogen ion implantation isolation processes were adopted to fabricate isolation regions in self-aligned GaN MISFETs for the first time. Maximum drain current of 98 mA/mm, maximum trans conductance of 10 mS/mm and threshold voltage of +0.4 V were obtained for the devices. The leakage current between adjacent devices was low, i.e., in the range of 10-6 mA/mm, which is three orders of magnitude lower than those on sapphire substrates. These supreme results indicate a definite availability of normally-off self-aligned GaN MISFETs for power switching device applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

This paper presents first results of a new high performance enhancement-mode (E-mode) gallium nitride (GaN) based metal-oxide semiconductor high electron mobility transistor (MOS-HEMT) that employs an ultrathin 3 nm aluminium gallium nitride (Al0.25G0.75aN) barrier layer and relies on an induced two dimensional electron gas (2DEG) for operation. Devices have been demonstrated on both sapphire and silicon substrates. Single finger devices on a sapphire substrate were fabricated using 10 nm and 20 nm, and on a silicon substrate using 30 nm of plasma enhanced chemical vapour-deposited (PECVD) silicon dioxide (SiO2) as the gate dielectric. They demonstrated threshold voltages of +3 V, +2 V, +0.8 V and very high maximum drain currents of over 620 mA/mm, 550 mA/mm and 450 mA/mm, respectively. These results show that the proposed device concept can be a building block for future power electronic devices. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Normally-off AlGaN/GaN HEMTs have been fabricated by employing a recessed-gate structure and oxygen plasma treatment and outstanding improvement of V variation is observed. The origin of the observed positive V shift and reduced variation window induced by oxygen plasma treatment is investigated by computational methods. Formation energy calculations for oxygen inclusions in III-N reveal that a negatively charged V- O complex in the AlGaN passivation layer can be a major source of V variation in AlGaN/GaN hetero-structured devices. Calculated trap energy levels are used as the parameters of a device simulation, which indicated that significant V variation can be induced by a small fluctuation in the AlGaN layer thickness and defect densities. Our theoretical investigation shows that normally-off AlGaN/GaN HEMTs having reliable V variation can be produced by oxygen inclusions accompanying a recessed-gate structure. [ABSTRACT FROM AUTHOR]

This paper describes normally-off GaN MOSFETs with high-k dielectric CeO2 films made by ion implantation. Ion implantation process reduces sheet and contact resistances of source and drain regions of this device. To obtain high Idss and gmmax, high-k dielectric CeO2 was used as gate oxide films for GaN MOSFETs for the first time. Nitrogen ion implantation isolation processes were also adopted to fabricate isolation region. Normally-off GaN MOSFETs with Idss of 350 mA/mm, gmmax of 40 mS/mm and threshold voltage of +0.5 V were obtained. The high Idss and normally-off mode show the potential and advantages of GaN MOSFETs for high voltage operations. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Abstract: Several types of GaN MOSFETs with normally-off operation have been fabricated on insulating substrate and evaluated. In recessed-gate GaN MOSFET, the threshold voltage (V th) can be easily controlled, but the current drivability is modest and needs to be improved by adopting appropriate device structure and/or process. We achieved enhanced performance by combining the recessed-gate technology with additional processes, such as: (i) the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, (ii) the post-deposition annealing of gate oxide to decrease the gate leakage current, (iii) the re-growth of n+-GaN layer for source/drain to improve the access resistance and V th uniformity, (iv) the stress-control technology to secure high 2-D electron–gas density (2DEG) on source/drain and decrease the series resistance, and (v) the use of the p-GaN back-barrier to decrease the buffer leakage current. We also present the characteristics of GaN-based FinFETs with very narrow fin. [Copyright &y& Elsevier]

We demonstrate MISFETs based on GaN p-epilayers with ion-implanted source/drain regions and atomic layer deposited (ALD) gate dielectrics of Al2O3 and HfO2. The fabrication technology is similar to that used for silicon MOSFETs. We find that there are significant shifts (of order 1 V) in threshold voltage between FETs produced with Al2O3 and HfO2 films, enabling depletion mode and enhancement mode device operation for the same substrate doping. The GaN MISFETs obtained maximum drain current of 580mA/mm and an extrinsic transconductance as high as 160 mS/mm. To the authors' knowledge, the transconductance achieved represents record performance for ion-implanted MISFETs of GaN without heterostructure barriers. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Abstract: We have grown high quality GaN layers on (111)-oriented silicon substrate using a two-step growth method and fabricated high-performance normally-off n-channel GaN Schottky-barrier MOSFET (SB-MOSFET). Indium-tin-oxide (ITO) was used as Schottky-barrier contact for source and drain (S/D) because the work function of ITO is close to the electron affinity of GaN. Due to enhanced crystalline quality and reduced surface roughness of GaN layer grown by two-step process, the fabricated device exhibited much improved performances: sufficiently high threshold voltage of 3.75V, subthreshold slope of 171mV/dec, low specific on-resistance of 9.98mΩcm2, and very high field-effect mobility of 271cm2/Vs. This is the highest mobility value among the GaN MOSFETs ever reported so far. [Copyright &y& Elsevier]

Abstract: We tried normally-off operation GaN metal–oxide–semiconductor field effect transistors (MOSFETs). n+ Contact layers as a source and drain region were fabricated using a Si ion implantation technique with the activation annealing at 1300°C for 30s in Ar ambient. The ohmic contact and sheet resistance of n+ contact layer were 1.1×10−7 Ωcm2 and 53Ω/sq, respectively. As a result, we achieved a normally-off operation GaN MOSFETs and moreover high temperature operation of 250°C for the first time. Threshold voltage (V th) was +3V. Drain current (I d) was over 100mA/mm at gate voltage (V g) of 10V and drain-to-source voltage (V ds) of 10V. Maximum field effect mobility (μ FE) was 210cm2/Vs at V ds =0.1V. [Copyright &y& Elsevier]

We have developed an AlGaN/GaN-on-Si metal–oxide–semiconductor heterojunction field-effect transistor (MOSHFET) integrated with a clamp circuit to enable normally-off operation. A clamp circuit consisting of a multilayer MIM capacitor and a Schottky barrier diode was monolithically integrated with a normally ON AlGaN/GaN MOSHFET. The integrated clamp circuit shifted the input driving signal from (0, 20 V) to (−19.2, 0.8 V), allowing the normally ON AlGaN/GaN MOSHFET with a pinchoff voltage of −14 V to be operated as a normally-off device. The multichannel device with a 5-mm channel width exhibited a drain current density of $\sim 470$ mA/mm and a breakdown voltage of >900 V. In comparison with other conventional normally-off GaN-based FETs, a higher threshold voltage with high current density (i.e., low ON-resistance) can be achieved with easy device processing, no need for gate recess or complicated epitaxial growth. [ABSTRACT FROM AUTHOR]

Normally off Al2O3/GaN MOSFETs are fabricated with a tetramethylammonium hydroxide (TMAH) treatment as a postgate recess etch. The effects of the surface treatment on the etched GaN surface are investigated using low-frequency (1/ f ) noise and capacitance–voltage ( C – V ) measurements. For a quantitative comparison with conventional devices, the oxide trap density ( ) is extracted using the unified 1/ f noise model, whereas the interface trap density ( D\mathbf {it} ) is extracted using the high–low-frequency C – V method. After the TMAH treatment, N_{\mathbf {ot}} is found to have decreased from 5.40 \times 10^{\mathrm {\mathbf {19}}} to 2.50 \times 10^\mathrm \mathbf 19~\mathrmeV^\mathrm \mathbf -1 \mathrmcm^\mathrm \mathbf -3 , whereas D\mathbf {it}^{\vphantom {(}} is decreased from 2.8 \times 10^\mathrm \mathbf 12 to 1.1 \times 10^\mathrm \mathbf 11~\mathrmeV^\mathrm \mathbf -1 \mathrmcm^\mathrm \mathbf -2 , as compared with conventional devices. The surface treatment is thus shown to lower trap density in the Al2O3/GaN MOSFETs by smoothing the surface and suppressing plasma damage in the recessed GaN surfaces. [ABSTRACT FROM AUTHOR]

A new high-performance normally-off gallium nitride (GaN)-based metal–oxide–semiconductor high electron mobility transistor that employs an ultrathin subcritical 3 nm thick aluminium gallium nitride (Al0.25Ga0.75N) barrier layer and relies on an induced two-dimensional electron gas for operation is presented. Single finger devices were fabricated using 10 and 20 nm plasma-enhanced chemical vapor-deposited silicon dioxide (SiO2) as the gate dielectric. They demonstrated threshold voltages (V \(_{\mathrm {\mathbf {th}}}\) ) of 3 and 2 V, and very high maximum drain currents (I \(_{\mathrm {\mathbf {DSmax}}}\) ) of over 450 and 650 mA/mm, at a gate voltage (V \(_{\mathrm {\mathbf {GS}}}\) ) of 6 V, respectively. The proposed device is seen as a building block for future power electronic devices, specifically as the driven device in the cascode configuration that employs GaN-based enhancement-mode and depletion-mode devices. [ABSTRACT FROM AUTHOR]

In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an off-state breakdown voltage of 600 V, and high on/off drain current ratio of \(\sim 10^{\mathrm {\mathbf {9}}}\) . [ABSTRACT FROM AUTHOR]

In this letter, reduction of threshold voltage instability in gate recessed normally-off GaN metal insulator semiconductor high electron mobility transistors with SiNx gate insulator was investigated. A plasma enhanced atomic layer deposition technique was successfully employed for very thin SiNx (5 nm) as an interfacial layer. The hysteresis and drift of threshold voltage in transfer curve and the forward biased gate leakage current were effectively reduced. [ABSTRACT FROM PUBLISHER]

• Monolithic integration of normally-off p-channel and n-channel HFETs were achieved based on a p-GaN gate Al 0.2 Ga 0.8 N/Al 0.05 Ga 0.95 N HFET platform. • The threshold voltage of p-channel HFETs can be adjusted by controlling the gate trench depth. • By using AlGaN channel instead of conventional GaN channel layer, the threshold voltage and the breakdown voltage were improved evidently. In this work, normally-off p-channel and n-channel heterojunction field-effect transistors (HFETs) were fabricated based on a p-GaN gate Al 0.2 Ga 0.8 N/Al 0.05 Ga 0.95 N HFET platform. For p-channel HFETs, normally-off operation and low gate leakage were obtained by using a recessed-gate structure and a 20 nm Al 2 O 3 thin film grown by thermal atomic layer deposition as the gate insulator. The normally-off p-channel HFETs exhibited a threshold voltage of <−0.9 V and a high on/off current ratio of >105. By introducing an Al 0.05 Ga 0.95 N channel instead of a conventional GaN channel layer, the threshold voltage increased from 1.1 V to 1.5 V and the breakdown voltage almost doubled from 270 to 580 V for n-channel HFETs. These results indicate that n-channel and p-channel HFETs based on p-GaN/Al 0.2 Ga 0.8 N/Al 0.05 Ga 0.95 N heterostructures have a great potential for monolithic integration. [ABSTRACT FROM AUTHOR]

Abstract: Normally-off GaN-MOSFETs with Al2O3 gate dielectric have been fabricated and characterized. The Al2O3 layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330mA/mm and the maximum transconductance of 32mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347mV/dec and from 50 to 55cm2 V−1 s−1, respectively. The I D–V G curve shows hysteresis due to oxide trapped charge in the Al2O3 before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750°C. The Al2O3 layer starts to crystallize at a temperature of 850°C and its insulating property deteriorates. [Copyright &y& Elsevier]

This letter reports normally-off operation of an AIGaN/GaN recessed MIS-gate heterostructure field-effect transistor with a high threshold voltage. The GaN-based recessed MIS-gate structure in conjunction with negative polarization charges under the gate allows us to achieve the high threshold voltage, whereas the low ON-state resistance is maintained by the 2-D electron gas remaining in the channel except for the recessed MIS-gate region. The fabricated device exhibits a threshold voltage as high as 5.2 V with a maximum field-effect mobility of 120 cm2 /V s, a maximum drain current of over 200 mA/mm, and a breakdown voltage of 400 V. [ABSTRACT FROM AUTHOR]

A gallium nitride (GaN)-based normally off metal–oxide–semiconductor field-effect transistor (MOSFET) using a dual-metal-gate (DMG) structure was proposed and fabricated to improve current drivability. Normally off operation with a high Vth of 2.3 V was obtained using a Cl2/BCl3-based recess etching process. The DMG structure was employed to improve current characteristics, which can be degraded by recess etching. The ID and gm of a DMG-based device with nickel (Ni)-aluminum (Al) were improved by 42.1% and 30.9%, respectively, in comparison to the performances of a single-metal-gate-based device with Ni because the DMG structure increased electron velocity in the channel region. This demonstrates that the DMG structure with a large work-function difference significantly improves the carrier transport efficiency. GaN-based recessed-gate MOSFETs based on the DMG structure hold promising potentials for high-efficiency power devices. [ABSTRACT FROM AUTHOR]

A tetramethyl ammonium hydroxide (TMAH)-treated normally-off Gallum nitride (GaN) metal-insulator-semiconductor field-effect transistor (MISFET) was fabricated and characterized using low-frequency noise (LFN) measurements in order to find the conduction mechanism and analyze the trapping behavior into the gate insulator as well as the GaN buffer layer. At the on-state, the noise spectra in the fabricated GaN device were 1/fγ properties with γ ≈ 1, which is explained by correlated mobility fluctuations (CMF). On the other hand, the device exhibited Lorentzian or generation-recombination (g-r) noises at the off-state due to deep-level trapping/de-trapping into the GaN buffer layer. The trap time constants (τi) calculated from the g-r noises became longer when the drain voltage increased up to 5 V, which was attributed to deep-level traps rather than shallow traps. The severe drain lag was also investigated from pulsed I-V measurement, which is supported by the noise behavior observed at the off-state. [ABSTRACT FROM AUTHOR]