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A simple yet effective approach for programmable gain amplifier (PGA) with a high precision decibel (dB)-linear characteristic and wide bandwidth is presented in this brief. This novel approach is presented by innovatively combining two techniques. Based on the binary-weighted switching technique, the circuit can approach an accurate pseudo-exponential function without using an additional exponential generator for gain control. By adopting the active feedback circuit structure, the bandwidth of PGA can be extended and it also contributes to improve the robustness, both of which cleverly reached a good consistency. The proposed PGA is fabricated in a $0.18~{\mu }\text{m}$ CMOS technology, the core circuit occupies an area of 0.11 mm2. Operated at a supply voltage of 1.8 V, the PGA consumes 8.21 mW. The measurement results show that the voltage gain of the proposed PGA can be controlled from −4.2 dB to 25.9 dB with a gain error less than ±0.09 dB, and the minimum −3dB bandwidth is almost 630 MHz. The input 1dB compression point is measured from −28.7 to 0.5 dBm, while the input referred noise is from 22.4 to 70.9 nV/ ${{\sqrt {}}}$ Hz. [ABSTRACT FROM AUTHOR]

This letter presents a 39-GHz phase-inverting variable gain power amplifier (VGPA) for 5G communication. Adopting a Gilbert structure-based variable gain amplifier (VGA) stage, the VGPA realized the dB-linear gain control characteristic as well as 180° phase inversion. At 0°/180° phase states, the 39-GHz VGPA achieves the maximum gain of 38.7/38.9 dB with gain tuning range of 5.6/5.2 dB, respectively. Over 38–43 GHz, the phase inversion error is limited within 5.9°, and the rms phase error is less than 3.6°/2.2°. Meanwhile, with the metal interleaving coplanar transformer matching network, this VGPA achieves 17.7/17.6-dBm Psat and 13.2/13.36-dBm OP1 dB, with the power added efficiency (PAE) of 35%/34.5% and 13.6%/14.4% at the saturation and 1-dB compression points, respectively. Over the gain control states, the OP1 dB fluctuation is less than 0.3 dB. Implemented in a 65-nm CMOS process, the proposed VGPA consumes 150 mW with a chip area of 0.3 mm2. [ABSTRACT FROM AUTHOR]

A 28 GHz dual-mode phase-invariant wide-dynamic-range variable-gain amplifier (VGA) with adaptive phase compensators is presented for use as a gain control element in a beamforming IC, which must have a small chip size and low power consumption. It consists of a single-stage differential amplifier with main and auxiliary signal paths, where the auxiliary paths are introduced to achieve most-significant-bit (MSB) gain control. The wide-gain dynamic range is also covered through a least-significant-bit (LSB) gain-control scheme, which is implemented with bias control of common gate (CG) transistors in the main signal paths. In addition, the phase variations due to the gain controls are drastically reduced by introducing phase compensators for both gain controls. The proposed VGA shows a gain dynamic range of 24 dB, maximum gain of 13 dB and root-mean-square (RMS) phase error of 2.77 degrees at 28 GHz. The maximum DC power consumption is 24 mW at the maximum gain, the minimum is 4 mW at the minimum gain, and the chip size is 0.066 mm2. [ABSTRACT FROM AUTHOR]

This article presents a neural-recording IC with automatic gain control (AGC) according to the input signal level. AGC enhances the dynamic range (DR) of the recording IC by more than 30 dB and allows it to take the benefits of the front-end amplification-based and direct-conversion-based recording structures concurrently. By adaptively controlling the analog front-end (AFE) gain, the input-referred noise (IRN) of the overall system is greatly reduced while ensuring a wide DR. A continuous-time (CT) dynamic-zoom $\Delta \Sigma $ ADC (CT-Zoom-ADC) is used for power-efficient two-step conversion. The coarse conversion output is reused for AGC, and the fine conversion resolution is adjusted adaptively by modifying the oversampling ratio according to the varying AFE gain. The presented neural-recording IC achieves 99.5-dB DR and 6.1- $\mu \text{V}_{\textrm {rms}}$ IRN over 5-kHz bandwidth, resulting in FoMDR of 185.2 dB, the effective number of bits (ENOB) of 11.4 bits, and tolerance against artifacts with differential voltage amplitudes up to 1.6 $\text{V}_{\text {pp}}$. Measurements with pulsatile artifacts and experiments in vivo validate that the proposed IC is applicable to the closed-loop neural interface. [ABSTRACT FROM AUTHOR]

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors ($C_{\mathrm {ds}}$) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of $C_{\mathrm {ds}}$ within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm2 excluding input–output pads. [ABSTRACT FROM AUTHOR]

This paper presents a digital processing system for terrestrial laser range finding systems. It is mainly comprised of a commercial digital signal processor with 400 MHz. For the signal digitization, an analog-to-digital converter with a 12-bit resolution is sampled with 50 MS/s. Such a digital system architecture has several advantages: automatic gain control, coherent multi-pulse averaging, digital signal filtering, upsampling, and advanced peak detection methods. When combined with a suitable laser and detector unit, the digital system outperforms the classic analog threshold-based laser finders with regard to required laser output power, multitarget discrimination, and peak detection accuracy. The best results were achieved using a matched filter, compared to wavelet denoising techniques and classic Savitzky-Golay filtering. Finally, this system architecture allows for a small-sized, lightweight, battery-operated, and energy-efficient, class 1 eye-safe laser range finder, capable of measuring distances up to multiple km with accuracy and precision of better than 1 m to uncooperative targets. [ABSTRACT FROM AUTHOR]

In this brief, we present a 28 GHz high slope automatic switching power detector system using a PMOS current-steering VGA and Schmitt trigger (ST) for 5G mobile communication. The forward RF path is composed of a four-stages variable gain amplifier and a buffer amplifier. The feedback path is composed of the power detector, two STs, and an inverter to achieve an automatic gain switching mechanism. The input RF small-signal is amplified by the RF path and converted to dc voltage by power detector. By feedback path to switch to different gain states, it can extend the overall dynamic range with high slope and avoid the system from saturation. Based on ±1 dB log error, the measured minimum detectable power and dynamic range are −47.2 dBm and 41.5 dB at 28 GHz. The peak slope value are 61/59/67 mV/dB under three modes. Total dc power consumption is only 35 mW for 1.8 V supplied voltage. To our best knowledge, this power detector system is the first time using the automatic switching technique in the millimeter-wave band power detector. It has better minimum detectable power, dynamic range, and the highest slope among published power detector systems. [ABSTRACT FROM AUTHOR]

A 60-GHz variable-gain active phase shifter using particular-sized digital-RF cells is proposed, which is fabricated using a 65-nm CMOS process. The phase shifter consists of an input buffer, an $I/Q$ generator, and vector-summing amplifiers with digital-RF cells. In a vector-sum phase shifter using a conventional tail current steering scheme, the operation regions of vector-summing amplifiers are changed with phase and gain states. Accordingly, their input impedances are altered significantly, which causes gain and phase imbalances of the $I/Q$ generator, especially around 0°, 90°, 180°, and 270°. This makes the rms phase and gain errors of the phase shifter increase. In this article, a vector-summing amplifier that always has a constant input impedance in all phases and gain states is proposed. A circular constellation and a dynamic range of more than 15 dB are implemented by using particular-sized digital-RF cells. The proposed phase shifter shows the rms gain and phase errors of < 0.29 dB and <2.01°, respectively, in a 10-GHz bandwidth of 55–65 GHz with 3-bit gain and 4-bit phase resolutions. The chip area and power consumption are 0.38 mm2 and 25.2 mW, respectively. [ABSTRACT FROM AUTHOR]

A Ka-band differential variable gain amplifier (VGA) applying symmetrical unit arrays with 6-bit digital-controlled is presented. The proposed VGA, based on the conventional current steering theory, uses symmetrical unit arrays that keep the output impedance constant, while digital-controlled voltage changes. Then it combines neutralizing capacitances to counteract the Miller effect of parasitic capacitances between gain and drain of input transistors. The VGA with symmetrical unit arrays ensures the consistency of phase variation during gain fluctuation. The VGA is fabricated in a 65-nm CMOS technology, and achieves −20.2 to −4.2 dB gain varied with 1.52 dBm IP1dB as well as 8.6 dB noise figure at 36 GHz and less than 4.9° phase variation, while consuming 15.6 mW across 30.5–39 GHz frequency range. [ABSTRACT FROM AUTHOR]

This brief proposes a variable gain power amplifier (VG-PA) with stable linearity for n257/n258 frequency band applications. A switched-capacitor array is proposed in the cascode (CC) circuit to control the gain while maintaining linearity. A compensation inductor is introduced between the common-emitter (CE) and common-base (CB) transistors to suppress the phase variation. For the proof of concept, the VG-PA was fabricated in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology with a core size of 0.59 $\times $ 0.46 mm2. Measurements show that at 24/26/28/29.5 GHz, over 5.7/5.5/7.0/7.5-dB gain tuning range, the output 1-dB compression point (OP1dB) is better than 14 dBm with $ {\Delta }$ OP1dB less than 1.2 dB, the third-order output intercept point (OIP3) is better than 22 dBm with $ {\Delta }$ OIP3 less than 3.4 dB, and the phase variation ($ {\Delta }{\varphi }$) is from 3 to 9.5°. To the author’s best knowledge, this work has the lowest linearity variation among Si-based variable gain amplifiers at millimeter-wave frequency band. [ABSTRACT FROM AUTHOR]

This brief presents a compact variable gain amplifier (VGA) with continuous time-gain compensation (TGC) for ultrasound imaging. The proposed VGA utilizes an open-loop topology and transconductance-subtraction load for compact implementation with sufficient gain range. To compensate for gain nonlinearity of VGA, this work proposes a systematic predistortion of gain-control signal to enhance an accuracy of TGC operation. The proposed VGA implemented in 180-nm CMOS process occupies 0.025 mm2, and consumes 0.96 mW for the maximum gain condition with a supply voltage of 1.8 V. A real-time continuous TGC has been illustrated in measurement. The fabricated VGA achieves a gain range of 37 dB, a gain error below 1.4 dB, and an input referred noise of 8.6 nV/ ${\surd }$ Hz for the maximum gain condition. [ABSTRACT FROM AUTHOR]

This article presents a 23–28-GHz digital-controlled phase-invariant and ultralow gain error variable gain amplifier (VGA) for 5G applications. The mechanisms of gain control and phase variation in CMOS VGA based on single-level transistor structure are analyzed in detail. According to the analysis, an active cross-coupling neutralization (ACCN) technique is proposed. The ACCN technique not only compensates for phase variation, but also makes phase compensation insensitive to the process, supply voltage, and temperature (PVT) variations. For achieving ultralow gain error, an asymmetric capacitive gain resolution improvement (ACGRI) technique is adopted, which realizes a fine gain step with low control circuit complexity. Further to reduce gain error, greatly improving the accuracy and robustness against PVT of gain control is necessary. With regard to this, a current-type digital-to-analog converter (DAC) is also integrated onto the chip. The proposed VGA is demonstrated in 65-nm CMOS technology with a core chip area of 0.14 mm2. Under 5-b digital gain control conditions, the presented VGA achieves a measured linear gain tunability range of 6.2 dB with a 0.2-dB fine tuning step. The measured root mean square (rms) phase error is less than 0.92° across 24–28 GHz with a minimum value of 0.63° at 27.8 GHz. The rms gain error is less than 0.13 dB, with a minimum value of only 0.03 dB at 25 GHz. At the maximum gain state, the proposed CS VGA exhibits a peak gain of 29.4 dB with 3-dB bandwidth of 23.5–27.5 GHz and the minimum noise figure is 4.8 dB at 26 GHz. Besides, the measured OP1dB and OP3dB are 6.3 and 9.6 dBm, respectively. The influence of VT variations on the phase compensation and gain tuning is also measured, and the proposed VGA exhibits strong robustness. [ABSTRACT FROM AUTHOR]

This letter presents a high precision wideband active vector-modulating phase shifter with high dynamic range gain control ability. Compared with conventional switching-filter phase shifter and vector-modulation phase shifter, this $\Delta $ – $\Sigma $ modulated vector phase shifter can provide quasi-continuous phase and gain control capability. According to the experimental results, the dynamic range of gain control is greater than 35.5 dB. The output reflection is lower than −10 dB through the 18–50-GHz band, and the input reflection is lower than −10 dB from 18 to 45 GHz. The phase shifter occupies 700 $\mu \text{m}\,\,\times $ 900 $\mu \text{m}$ on 0.13- $\mu \text{m}$ SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology, and the core size is only $400\,\,\mu \text{m}\,\,\times 500\,\,\mu \text{m}$. After digital calibration, the proposed phase shifter has achieved the highest phase and gain control precision compared with the state-of-the-art digital controlled phase shifters. [ABSTRACT FROM AUTHOR]

This letter presents a dual-polarization beamformer chip for fifth-generation (5G) applications. The chip leverages a vector-sum phase shifter (VSPS) approach and single-ended design, allowing a reduced control circuitry complexity. The use of the VSPS translates in both phase shift and gain control, as shown in the system analysis. This beamformer is suitable for four dual-polarized antennas, achieving high gain control for each element. The performance can be summarized as a 1-dB compression point of 11dBm, while having an rms phase and amplitude error lower than 0.5° and 0.4 dB, respectively, at the maximum constant magnitude gain circle. Moreover, it is shown that the design can afford tapering despite relying only on the VSPS for gain control. [ABSTRACT FROM AUTHOR]

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm2. It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is −27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz. [ABSTRACT FROM AUTHOR]

A Ka-band variable-gain phase shifter (VGPS) using a multi-vector summation method is proposed, which represents both phase and amplitude by summing the I and Q signals of multiple vectors. The VGPS has an orthogonal phase and gain control function with a wide gain-control dynamic range because it is designed to keep the input and output impedances almost constant regardless of the control states. It shows a measured RMS phase error of 2.9 ° during 17.3 dB gain control and that of 3.5 ° during simultaneous 17.3 dB gain and 360 ° phase control without any calibration from 30 to 32.5 GHz. The measured average insertion loss ranges from −4 to −2.8 dB from 28 to 33 GHz. It is implemented in a 65-nm RF CMOS process with the size of 0.21 mm2 excluding pads. [ABSTRACT FROM AUTHOR]

A K-band variable-gain phase shifter using a Gilbert-cell vector synthesizer with a current digital-to-analog converter (DAC) and an RC–RL poly-phase filter (PPF) is presented, which is fabricated with a 65-nm RF CMOS process. It controls both gain and phase with low phase and gain variations as well as a low insertion loss. The Gilbert cell synthesizes a vector by summing in-phase (I) and quadrature (Q) phase signals of which the amplitudes are decided by the tail currents of the summing cells, respectively. The tail currents are given by current DACs, which are particularly designed to make the synthesizer have a constant output impedance in all phase and gain states. Because the gain and phase control resolutions depend on those of the current DACs, the size and insertion loss of the variable-gain phase shifter are not dependent on the control resolutions. The total root-mean-square (rms) phase and gain errors are measured to be 0.488° and 0.098 dB for 4096 states of the 7-bit 360° phase and 5-bit 17.8-dB gain controls, respectively, which are calibrated with extra 2-phase and 1-gain control bits. It shows −3.5 dB maximum gain including ON-chip balun losses with 6.6-mW dc power consumption. [ABSTRACT FROM AUTHOR]

This study presents the design and analysis of a 60-GHz low-power active vector-sum phase shifter with 5-bit phase resolution. An impedance-invariant variable gain amplifier (VGA) is proposed and applied to the vector modulator. The proposed VGA not only demonstrates low phase and impedance variations during gain control but also high linearity under low supply voltage. Moreover, it reduces the gain/phase error in vector modulation. In addition, the transformer-based current-reuse technique is adopted to enhance the gain of the phased array channel while consuming low dc power. The prototype circuit implemented in 65-nm CMOS technology consumes only 5 mW of dc power and occupies an area of 0.3 mm2 (excluding pads). The measurement results of the prototype circuit reveal that the proposed phase shifter achieves an average gain of −3.8 dB (including a 2-dB loss of the measurement balun), an rms gain error of 0.25–0.72 dB, and an rms phase error of 3°–7° in the 3-dB bandwidth from 51 to 66.3 GHz. The measured input 1-dB compression point is observed to be higher than −1.1 dBm at 60 GHz. [ABSTRACT FROM AUTHOR]

This brief presents a W-band 6-bit active phase shifter fabricated in 0.13 μm SiGe BiCMOS process. A wideband quadrature signal generator composed of a 90-degree hybrid and a pair of transformers is exploited for low insertion loss and superior balance. Conventional architecture used in gain control unit is replaced by a novel phase inverter-embedded variable gain amplifier to achieve a high gain and low complexity. In addition, a balun-first combiner with symmetrical layout is utilized at the output to keep as low the imbalance of I/Q paths as possible. The proposed phase shifter exhibits a record average gain of 7 dB at 79 GHz with a 3-dB bandwidth from 71.5 to 84.5 GHz. The variation of gain remains below 2.1 dB over 64 phase states. The measured RMS phase error is 1.35° at 78 GHz and remains below 3.5° from 72 to 82 GHz. The RMS gain error is measured to be 0.46 dB at 75 GHz and keeps less than 0.76 dB from 71 to 82 GHz. The measured input 1dB compression point amounts to −10 dBm. To the best of the author’s knowledge, this brief presents the lowest RMS phase error (1.35°) and the highest gain (7 dB) compared with the reported silicon-based W-band active phase shifters. [ABSTRACT FROM AUTHOR]

We present a burst-mode receiver (BMRx) whose architecture and design is optimized for linear operation up to 25Gbaud modulation rates. The linear burst-mode receiver (LBMRx) consists of a fixed-gain transimpedance amplifier, followed by a three-stage post-amplifier and a 50-ohm output buffer. The gain of the post-amplifier stages and dc-offsets of the datapath can be quickly adjusted from one burst to the next through combined feedforward (providing rapid settling) and feedback (providing accurate gain and offset control) automatic-gain-control (AGC) and automatic-offset-control (AOC) loops. When receiving 25G NRZ and assembled with a PIN photodetector, a sensitivity of −18.1 dBm and overload of at least 3.5 dBm was measured at a bit-error-rate (BER) of 1E−2, thus supporting a 21.6 dB input dynamic range. When receiving 4-level pulse amplitude modulation (PAM-4), a sensitivity of −11.4 dBm and overload of at least 4.4 dBm was measured at a low-density-parity-check (LDPC) BER reference of 1E−2, supporting 15.8 dB dynamic range. Between −10 up to 3.5 dBm the LBMRx also features internal start-of-burst (SOB) and end-of-burst (EOB) detection. Over the specified input dynamic range, the total harmonic distortion (THD) remains below 5%. The receiver was designed in a 0.25 $\mu \text{m}$ SiGe:C BiCMOS technology, occupying an area of $1.32\times 1.05$ mm2 and consumes 280 mW from a 2.5 V supply. This LBMRx can be used as front-end for new upcoming passive optical networks (PONs) that may require, e.g., electronic equalization (to overcome bandwidth limitations of opto-electronic components) or dispersion compensation; or may be used to support advanced modulation formats requiring linear operation. [ABSTRACT FROM AUTHOR]

This article presents a wideband 120-GHz variable-gain amplifier (VGA) with a multistage phase compensation technique. The proposed multistage VGA consists of two different current-steering VGAs: one with a series inductor to improve gain performance and another with a shunt inductor to compensate for phase variation. To verify the proposed design, a 120-GHz VGA was fabricated utilizing a 40-nm CMOS technology with a compact size of 0.62 mm ${\times } 0.38$ mm, including pads. Under 2-bit control bias conditions, the proposed VGA provides controlled gains of 0, 2.9, 5.4, and 8.3 dB at a frequency of 120 GHz. In the maximum gain state, the VGA exhibits a peak gain of 12.3 dB while maintaining a 37-GHz bandwidth. Based on complementary phase compensation, the VGA achieves a maximum phase error of 5° within a gain control range of 8.3 dB and an in-band phase variation of 8.5° for a wide frequency range of 100–133 GHz. Under these conditions, the total power consumption is 31.2 mW at a supply voltage of 1.25 V. [ABSTRACT FROM AUTHOR]

Upstream burst-mode (BM) reception in a passive optical network (PON) creates unusual bit error patterns. We evaluate a model of burst-mode signal recovery, and experimentally demonstrate fast decision threshold tracking via digital equalization for 25-Gb/s BM reception. [ABSTRACT FROM AUTHOR]

This article presents a low-power CMOS digitally controlled variable gain low-noise amplifier (VGLNA) at $V$ -band in a 40-nm LP CMOS process. There are three amplifier stages and three digital gain control bits in this VGLNA. The first stage is a common source amplifier, and the second and third stages are current-reused amplifiers. In order to save dc power and control gain, we use the current-reused technique and add the digital switch between upper and lower transistors. Due to constant dc current, the input impedance of the current-reused stage is stable. Output impedance is stabilized by an ac grounding capacitor at the source terminal of the upper transistor under gain switching. Thus, our proposed VGA can minimize the interstage influence with the previous and following stage and maintain OP1dB due to the constant bias current. By adding a resonated inductor to cancel out the parasitic capacitance of switch transistor, we can keep bandwidth and improve noise figure (N.F.) at the current-reused stages under different gain states. The measured peak gain is 19.8 dB at 59.6 GHz, and lowest N.F. is 5.98 at 63.5 GHz. The gain states are 19.8/15.3/11.5/6.5 dB, respectively, and the measured input/output return loss is stable under different gain states. The IP1dB is increased from −29.5 to −17 dBm, and the OP1dB is nearly constant under different gain states. Total dc power consumption is only 18 mW for 1.1-V supplied voltage. This is the first digital current-reused VGLNA that has good FoM among digital VGLNA, the lowest dc power consumption, and compact die area at $V$ -band. [ABSTRACT FROM AUTHOR]

A 40-GHz variable gain amplifier (VGA) with 4-bit digital gain control and low phase variation is designed and fabricated on the 65-nm CMOS process. The digital gain control mechanism is achieved using the presented digital version current steering topology. The measured gain of the VGA is between 22 and 6 dB at 40 GHz with 16 different linear-in-decibel gain states. Using the proposed two-stage digital version current steering VGA phase compensation technique, the measured phase variation is 3.18° within a 16-dB gain control range (GCR) and the root mean square (rms) phase error is 0.89° at 40 GHz. [ABSTRACT FROM AUTHOR]

This brief presents a low noise, high dynamic range (DR), high linearity, and high selectivity analog baseband (BB) for multi-standard TV applications. A customized sixth-order low pass filter with two additional zeroes Chebyshev-I filter is adopted to enhance the average adjacent channel rejection (ACR) and the attenuation at 5.25 MHz, and a novel programmable gain amplifier (PGA) realizes accurate gains with a fine-tuning gain step of 0.25 dB. The digitally assisted real-time dc offset cancellation (DCOC) loop can prevent the BB chain from saturation robustly with a low residual output dc offset voltage (DCOV) and an extremely low cut-off frequency. The digitally assisted complementary cumulative distribution function (CCDF)-based on-chip automatic gain control (AGC) loop implements reliable amplitude control for digital TV signals with a large peak to average power ratio (PAPR). The BB chain fabricated in a 0.18 ${\mu }\text{m}$ CMOS process occupies an area of 1.2 mm2 and consumes a current of 21.3 mA from 1.8-V supply including the output buffer. It achieves a maximum gain of 62 dB and a DR of 68 dB with 0.25 dB minimum step. The attenuation at 5.25 MHz is 48.6 dB and the average ACR is 38.2 dB. The measured equivalent input-referred noise voltage is 22 ${\mathrm{ nV/}}\sqrt {\mathrm{ Hz}} $ , out-of-band IIP3 of 37.61 dBV, and out-of-band IIP2 of 77.19 dBV at 56 dB gain. The residual output DCOV is less than 5 mV and the minimum 3 dB cut-off frequency is 100 Hz when BB operates in the maximum gain of 62 dB. [ABSTRACT FROM AUTHOR]

This paper presents a read-out front-end application-specific integrated circuit (ASIC) for the measurement of tissue impedances. The 10 mm2 2-channel front-end ASIC is fabricated in a 0.18 μm CMOS technology. The measurement results show that the proposed ASIC operates over a frequency range of 100 Hz up to 10 MHz. The ASIC has 1.22 pW/Hz power performance, with an SNR over 72 dB for frequencies $\leq$ 1 MHz, and over 65 dB SNR for frequencies $\geq$ 1 MHz. The total measured power consumption of the read-out front-end is shown to range from 2.1 to 21.7 mW depending on the input frequency. To achieve a wide dynamic range, the instrumentation amplifier has an adaptive gain control feature, and it employs programmable bias currents and reconfigurable structure to save power while processing low-frequency signals. A dual digital-to-analog converter (DAC) hybrid SAR analog-to-digital converter (ADC) is presented that reduces the power consumption of the ADC driver by sevenfold for frequencies between 4 kHz and 1 MHz. [ABSTRACT FROM AUTHOR]

This paper investigates gain controllability of cladding- and core-pumping hybrid-pumped single-stage and double-stage multi-core (MC) erbium-doped amplifiers (EDFAs) for changes in the input signal power per channel and number of channels. During the gain control, the core-pumping power is adjusted, whereas the cladding-pumping power is kept constant. Static characteristics are experimentally measured, and both kinds of hybrid-pumped MC-EDFAs are gain controlled with a small gain change for both the input signal changes. Dynamic characteristics are investigated by calculating the gain transient response of a surviving channel of the gain-controlled hybrid-pumped MC-EDFAs for signal channel dropping, and the response characteristics are compared with those of reference EDFAs whose erbium-doped fiber (EDF) has the same core parameters as those of EDF used in a conventional practical EDFA. It is shown that there is no significant difference in dynamic gain controllability between the hybrid-pumped MC-EDFAs and reference EDFAs even though the cladding-pumping power is not adjusted and kept constant. The results for the static and dynamic gain control characteristics suggest that constant cladding-pump power has little impact on gain controllability of the hybrid-pumped MC-EDFAs. [ABSTRACT FROM AUTHOR]

This brief presents a new digitally assisted vector-summing phase shifter (DA-VSPS) featuring high accuracy and enhanced linearity. It begins by highlighting the RF performance degradation of traditional DA-VSPSs operating at millimeter-wave frequencies due to the large number of unit-cells and the significant underlying parasitics. Then, a new DA-VSPS topology is proposed to mitigate this source of performance degradation using analog variable-gain amplifiers with digitally assisted current sources. A study of the accuracy and linearity of the proposed DA-VSPS is conducted to inform the choice of the optimal parameters (number of unit-cells and load impedance) that maximize the RF performance while minimizing the implementation complexity. A proof-of-concept prototype was implemented in 45 nm silicon-on-insulator CMOS technology. The measurement results demonstrated a 1-dB RF bandwidth from 27 to 33 GHz, root-mean-square magnitude and phase errors of 0.1 dB and 0.5° to 0.6°, respectively, while covering 360° of phase shifts at 5° resolution. Furthermore, the measured group delay and input 1dB compression point are maintained within ± 4 ps and >2.2 dBm, respectively, at any phase shift settings. [ABSTRACT FROM AUTHOR]

Erbium-doped fiber amplifiers are a promising solution for the signal amplification in long-haul mode-division multiplexed transmission systems. In order to minimize signal degradations by these amplifiers, low mode dependent gain and noise figures are desirable. We propose a scalable mode dependent gain equalization scheme for the 1480-nm pump wavelength. Contrary to the 980-nm pump wavelength, each signal mode has a maximum overlap with only one pump mode. Due to this, a scalable mode selective gain control is achievable by adjusting the pump modes. In this letter, we demonstrate the scalability of our approach with the number of signal modes by numerical simulation. Furthermore, we propose a two-stage amplifier setup in which the mode dependent gain of both stages is compensated in the second stage, pumped at a wavelength of 1480 nm. [ABSTRACT FROM AUTHOR]

A programmable-gain amplifier with low power consumption is presented. The programmable gain function is achieved by varying the effective transconductance ratios of input and output stages, which is realized through innovative binary-weighted and triode-region transistor ladder. The proposed technique effectively overcomes the problems associated with the implementation of resistors ladder in these types of structures. The operational principle of this unique structure is discussed, its most important formulas are derived, and its outstanding performance is verified by post-layout simulations in TSMC 0.18- $\mu$ m N-well CMOS fabrication process. Owing to its unique construction, the proposed circuit combines the ever interesting constant bandwidth, linear-in-decibel, and fine-step programmable gain range merits all in a simple and low power structure. The core of proposed structure draws only 36.5 $\mu$ W from 1.8-V power supply. The circuit is capable of delivering a wide programmable range of about 37 dB and operating at frequencies up to 20 MHz. To approve the robustness of the structure, full process, voltage, and temperature variation analysis of the circuit is investigated through corner case and Monte Carlo simulations. Monte Carlo simulations show standard deviation values of less than 0.21 $\mu$ W and 0.5 dB in power consumption and voltage gain, respectively. These results indicate that the proposed structure would lend itself well for use in applications that demand high ratios of frequency over power consumption. [ABSTRACT FROM AUTHOR]

A differential variable gain amplifier (VGA) for wideband baseband signals has been designed, analyzed, and implemented in a 0.25- \rm \mu m InP double heterojunction bipolar transistor technology with f_{T}/f_{\mathrm{ max}} of 370/650 GHz. The 3-dB frequency bandwidth is measured to be 40 GHz with a maximum gain of 31 dB, resulting in a gain bandwidth product (GBP) of 1.4 THz, four times higher than previously reported GBP from a Gilbert cell-based VGAs. Furthermore, it measures a gain control range of 44 dB, a noise figure of 6.2 dB, an output third-order intercept point of 17 dBm, and a total power consumption of 350 mW from a single −7-V supply. With pseudorandom binary sequence test pattern signals, a clear open eye at 44 Gb/s was observed. The complete circuit, including on-chip integrated bias network and pads, measures 0.77 \rm mm^{2}$ . We analyze the VGA for the 3-dB bandwidth and GBP by the use of zero-value time constants method to analytically identify the maximum GBP with respect to the design parameters and current bias. [ABSTRACT FROM AUTHOR]

This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance techniques employed include a fully adaptive continuous-time linear equalizer, automatic gain control, an 11-tap decision feedback equalizer, wideband LC phase-locked loops, and a high-tracking-bandwidth clock and data recovery loop with low latency. Low-power techniques such as half-rate clocking, active inductors and data-rate programmability are employed to meet stringent power budgets at the different rates. At 16.3 Gb/s, the receiver has a jitter tolerance of >0.3UI at 100 MHz. The transceiver achieves a bit error rate < 10e − 15 with up to 28-dB loss at Nyquist. It consumes 219 mW/channel at 16.3 Gb/s. The design has robust performance across process, voltage, and temperature, and the architecture allows for a high degree of tuning to handle different system environments in deployment. [ABSTRACT FROM AUTHOR]

An assessment of non-geophysical effects in spaceborne global navigation satellite system reflectometry (GNSS-R) data from the UK TechDemoSat-1 (TDS-1) mission is presented. TDS-1 was launched in July 2014 and provides the first new spaceborne GNSS-R data since the pioneering UK-disaster monitoring constellation experiment in 2003. Non-geophysical factors evaluated include ambient L-band noise, instrument operating mode, and platform-related parameters. The findings are particularly relevant to users of uncalibrated GNSS-R signals for the retrieval of geophysical properties of the Earth surface. Substantial attitude adjustments of the TDS-1 platform are occasionally found to occur that introduce large uncertainties in parts of the TDS-1 GNSS-R dataset, particularly for specular points located outside the main beam of the nadir antenna where even small attitude errors can lead to large inaccuracies in the geophysical inversion. Out of eclipse however, attitude adjustments typically remain smaller than 1.5°, with larger deviations of up to 10° affecting less than 5% of the overall sun-lit data. Global maps of L1 ambient noise are presented for both automatic and programmed gain modes of the receiver, revealing persistent L-band noise hotspots along the Equator that can reach up to 2.5 dB, most likely associated with surface reflection of signals from other GNSS transmitters and constellations. Sporadic high-power noise events observed in certain regions point to sources of human origin. Relevant conclusions of this study are that platform attitude knowledge is essential and that radiometric calibration of GNSS-R signals should be used whenever possible. Care should be taken when considering using noise measurements over the equatorial oceans for calibration purposes, as ambient noise and correlated noise in delay–Doppler maps both show more variation than might be expected over these regions. [ABSTRACT FROM PUBLISHER]

This letter presents a Ka-band variable-gain amplifier (VGA) with low output 1-dB compression point (OP1dB) variation for 5G applications. The VGA comprises a cascode current-steering amplifier and a common source amplifier with capacitance neutralization and uses dual current steering to maintain a constant OP1dB. Implemented in a 65-nm CMOS technology, the proposed VGA consumes 8 mW and occupies a core chip area of 0.34 mm $\times0.49$ mm. The proposed VGA achieves a power gain of 21.2 dB at 27.5 GHz and a 3-dB bandwidth of 25.75–29.25 GHz. With the dual current-steering technique, the OP1dB of the fabricated VGA was measured as −1.4 to −0.2 dBm at 27–29 GHz for all gain states. [ABSTRACT FROM AUTHOR]

A variable-gain low-noise amplifier implemented in a 65-nm CMOS process for a beamforming front-end chip is presented, of which the phase remains constant during gain variations. The phase compensation characteristic is achieved by introducing a shunt PMOS and a parallel resistor at the differential outputs of common-gate (CG) transistors. This allows the gain to be controlled without phase variation by adjustment of the combined gate voltage of the CG transistor and the shunt PMOS at the same time. The proposed device shows a gain of 20.8 dB and a noise figure of 3.71 dB at 31 GHz. It shows a root-mean-square phase error of less than 3° over the gain control range of 10.6 dB at 30–34.5 GHz. [ABSTRACT FROM AUTHOR]

A 12 GHz VGA showing a gain variation range from -9\;\textdB to 13\;\textdB with a linear-in-dB gain control feature is presented in this work. As the gain is changed, the phase shift over the entire 10–14.4 GHz bandwidth varies as little as \leq 2° due to a compensation circuitry that reduces the input-output phase shift sensitivity to gain variations in a robust manner with respect to temperature changes. Such a reduced phase shift variation is particularly useful to simplify the signal phase/amplitude control for the various paths of a phased array system, and allows to implement ultra-low sidelobe phased arrays. The VGA prototypes, implemented in a SiGe bipolar technology, show a noise figure of 5.1 dB, an IIP3 of - 3\;{\rm dBm}, a {P_{1{\rm dB}}}$ of - 17\; \text{dBm}, and a power consumption of 83 mW. [ABSTRACT FROM PUBLISHER]

This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang–bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves $<\! 290$ fs integrated rms jitter and $<\! - 72.89$ dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of $- 245$ dB. [ABSTRACT FROM PUBLISHER]

This work presents an inductorless, 10 Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator, and a novel exponential function generator for extended dB-linear performance. Third-order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10 Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of \sim40\;\textdB with better than \pm 1\;\textdB gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for 2^31-1 PRBS input, maintaining 360\;\textmV_\textp-p constant differential output with a BER <10^-12 for an input dynamic range of \sim24\;\textdB (15–240 \textmV_\textp-p). Fabricated in IBM 0.13 \upmu \textm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of 0.4\;\textmm^2. [ABSTRACT FROM PUBLISHER]

A 60-GHz digitally controlled phase-inverting variable gain amplifier (PIVGA) is presented, with a gain control range from −9.4 to 6 dB, and a 180° phase inversion. Four digitally controlled nMOS switch arrays in the proposed PIVGA are used as a current-steering stage, which can reduce control complexity of the current-steering stage and reduce phase variation as well. A transformer to decouple input stage and current-steering stage instead of the nMOS transistor cascode topology is used to improve linearity. The PIVGA prototype is implemented in a 65-nm CMOS technology. Measured results show a gain range from −1 to 6 dB with a 0.5-dB linear-decibel fine gain step, an OP1 dB of 0 dBm, and a dc power consumption of 25 mW. As the gain is programmed over the entire 53–63 GHz, the phase shifts only varies by less than 3°. [ABSTRACT FROM AUTHOR]

This paper presents a high power efficient broad-band programmable gain amplifier with multi-band switching. The proposed two stage common-emitter amplifier, by using the current reuse topology with a magnetically coupled transformer and a MOS varactor bank as a frequency tunable load, achieves a 55.9% peak power added efficiency (PAE), a peak saturated power of +11.1 dBm, a variable gain from 1.8 to 16 dB, and a tunable large signal 3-dB bandwidth from 24.3 to 35 GHz. The design is fabricated in a commercial 0.18-\mum SiGe BiCMOS technology and measured with an output 1-dB gain compression point which is better than +9.6 dBm and a maximum dc power consumption of 22.5 mW from a single 1.8 V supply. The core amplifier, excluding the measurement pads, occupies a die area of 500 \mu\ m\times \ 450~\mu\ m. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS broadband programmable gain active balun (PGAB) that demonstrates seven digitally controlled gains with 0.5-dB gain steps separately for plus and minus output ports. The PGAB was designed and fabricated in a 130-nm RFCMOS process. For the maximum gain state, the measured gains of the plus and minus ports are 0.0 and 1.1 dB at 2 GHz. The operating frequency range is from 1.0 to 8.0 GHz by 0.3-dB gain step error, and it is from 1 to 13.0 GHz by 3-dB gain attenuation. For the maximum gain state, the measured amplitude imbalance and phase imbalance from 1 to 16 GHz are less than 1.4 dB and 4.1^\circ, respectively. The measured input return losses are better than 13.5 dB, and the output return losses are better than 18.5 dB for all controlled gain states from 1 to 16 GHz. The measured IP1dB at 7 GHz is 6.1 dBm. The measured noise figures for the plus and minus ports from 2 to 14 GHz are less than 11.2 and 10.2 dB, respectively. The supply voltages are 3.0 and 1.5 V, and the measured power consumption is 93 mW. The core area of the fabricated integrated circuit is 0.38 mm\,\times\,0.36 mm. [ABSTRACT FROM AUTHOR]

This paper describes a 0.5–16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER < 10^-15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes. [ABSTRACT FROM PUBLISHER]