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This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53–0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7–2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than −74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power. [ABSTRACT FROM AUTHOR]

A D-band CMOS transmitter is presented with an integrated injection-locked frequency-tripling synthesizer, digital control, and an on-chip antenna. It employs an IF feed-forward pre-distortion scheme, which improves gain compression of the transmitter to provide an overall higher linearity gain profile, allowing reduced power back-off for higher peak-to-average modulation schemes. The integrated D-band transmitter consumes 347 mW and occupies 1800\,\times\,1500 \mu\ m of silicon area. The proposed transmitter delivers 0.4 dBm of effective isotropic radiated power with a saturated power on-chip of at least 12.2 dBm. The transmitter has a peak power-added efficiency (PAE) of 4.8% with power delivered to the antenna and a peak PAE of 0.31% when considering radiated power. [ABSTRACT FROM AUTHOR]