A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology.

This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53–0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7–2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than −74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power. [ABSTRACT FROM AUTHOR]