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The design optimization of multigate bulk MOSFET structures is investigated for sub-20-nm gate lengths. Three-dimensional device simulations were used to optimize device design parameters such as the retrograde channel doping profile, as well as the length, width, and height of the gated channel region. Compared with the FinFET design, the results indicate that the tri-gate MOSFET design is promising for continued bulk-Si CMOS transistor scaling, because it can achieve similar on-state current performance and intrinsic delay [for the same channel stripe pitch (SP)] at a lower height/width aspect ratio (0.8 versus 2.17) and less aggressive retrograde channel doping gradient for improved manufacturability. Only by increasing the height of the channel region and/or reducing the channel SP can the FinFET bulk MOSFET design achieve better delay, but at the cost of reduced manufacturability. [ABSTRACT FROM AUTHOR]

The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggressively scaled FinFETs are studied for different stressor technologies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is \1.5\times larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the channel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected. [ABSTRACT FROM PUBLISHER]

The impact of body-thickness scaling on strain-induced carrier-mobility enhancement in thin-body CMOSFETs with high-k/metal gate stacks, based on quantum-mechanical simulations calibrated with measured data, is presented to provide insight into device performance enhancement trends for future technology nodes. [ABSTRACT FROM AUTHOR]